tree a6eec9f88741935b64ae39157a42f17aab48878e
parent 2bf2ee5fbf2e152f6597d660c7d03457cc5fb4b3
author Marek Vasut <marex@denx.de> 1459797378 +0200
committer Marek Vasut <marex@denx.de> 1461144525 +0200

ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>