tree 2f4e9d5515b5db81a3f9a09c64a1e18d81832bda
parent 16189d6c8b67c0240ef932235250e955a1113d7f
author Marek Vasut <marex@denx.de> 1590797688 +0200
committer Stefano Babic <sbabic@denx.de> 1591605774 +0200

ARM: imx: ddr: Add missing PHY reset

The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
explicitly says both the DDR controller and the PHY must be reset in the
correct sequence. Currently the code only resets the controller. This
leads to a misbehavior where the system brings the DRAM up after reboot,
but the DRAM is unstable. Add the missing reset.

The easiest way to trigger this is by triggering WDT without having the
WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>