arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/mach-mediatek/mt7629/Makefile b/arch/arm/mach-mediatek/mt7629/Makefile
new file mode 100644
index 0000000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7629/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c
new file mode 100644
index 0000000..ba91a6e
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7629/init.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <linux/io.h>
+
+#include <dt-bindings/clock/mt7629-clk.h>
+
+#define L2_CFG_BASE 0x10200000
+#define L2_CFG_SIZE 0x1000
+#define L2_SHARE_CFG_MP0 0x7f0
+#define L2_SHARE_MODE_OFF BIT(8)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mtk_pll_early_init(void)
+{
+ unsigned long pll_rates[] = {
+ [CLK_APMIXED_ARMPLL] = 1250000000,
+ [CLK_APMIXED_MAINPLL] = 1120000000,
+ [CLK_APMIXED_UNIV2PLL] = 1200000000,
+ [CLK_APMIXED_ETH1PLL] = 500000000,
+ [CLK_APMIXED_ETH2PLL] = 700000000,
+ [CLK_APMIXED_SGMIPLL] = 650000000,
+ };
+ struct udevice *dev;
+ int ret, i;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
+ if (ret)
+ return ret;
+
+ /* configure default rate then enable apmixedsys */
+ for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
+ struct clk clk = { .id = i, .dev = dev };
+
+ ret = clk_set_rate(&clk, pll_rates[i]);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret)
+ return ret;
+ }
+
+ /* setup mcu bus */
+ ret = uclass_get_device_by_driver(UCLASS_SYSCON,
+ DM_GET_DRIVER(mtk_mcucfg), &dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ /* initialize early clocks */
+ ret = mtk_pll_early_init();
+ if (ret)
+ return ret;
+
+ ret = uclass_first_device_err(UCLASS_RAM, &dev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int mach_cpu_init(void)
+{
+ void __iomem *base;
+
+ base = ioremap(L2_CFG_BASE, L2_CFG_SIZE);
+
+ /* disable L2C shared mode */
+ writel(L2_SHARE_MODE_OFF, base + L2_SHARE_CFG_MP0);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_RAM, &dev);
+ if (ret)
+ return ret;
+
+ ret = ram_get_info(dev, &ram);
+ if (ret)
+ return ret;
+
+ debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
+
+ gd->ram_size = ram.size;
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ void __iomem *chipid;
+ u32 hwcode, swver;
+
+ chipid = ioremap(VER_BASE, VER_SIZE);
+ hwcode = readl(chipid + APHW_CODE);
+ swver = readl(chipid + APSW_VER);
+
+ printf("CPU: MediaTek MT%04x E%d\n", hwcode, (swver & 0xf) + 1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mediatek/mt7629/lowlevel_init.S b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
new file mode 100644
index 0000000..90dd4ea
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7629/lowlevel_init.S
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+
+#ifndef CONFIG_SPL_BUILD
+ /* Return to U-Boot via saved link register */
+ mov pc, lr
+#else
+ /*
+ * Arch timer :
+ * set CNTFRQ = 20Mhz, set CNTVOFF = 0
+ */
+ movw r0, #0x2d00
+ movt r0, #0x131
+ mcr p15, 0, r0, c14, c0, 0
+
+ /* enable SMP bit */
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x40
+ mcr p15, 0, r0, c1, c0, 1
+
+ /* if MP core, handle secondary cores */
+ mrc p15, 0, r0, c0, c0, 5
+ ands r1, r0, #0x40000000
+ bne go @ Go if UP
+ ands r0, r0, #0x0f
+ beq go @ Go if core0 on primary core tile
+ b secondary
+
+go:
+ /* master CPU */
+ mov pc, lr
+
+secondary:
+ /* read slave CPU number into r0 firstly */
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #0x0f
+
+loop:
+ dsb
+ isb
+ wfi @Zzz...
+ b loop
+#endif
+ENDPROC(lowlevel_init)