am33xx: Clean up unused DDR defines, prefix more with 'DDR2'
- Remove a handful of unused defines.
- Prefix more values with 'DDR2' as DDR3 will require different values.
Signed-off-by: Tom Rini <trini@ti.com>
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 12f270a..684b123 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -112,22 +112,22 @@
struct sdram_timing tmg;
struct ddr_phy_control phyc;
- /*Program EMIF0 CFG Registers*/
- phyc.reg = EMIF_READ_LATENCY;
- phyc.reg_sh = EMIF_READ_LATENCY;
- phyc.reg2 = EMIF_READ_LATENCY;
+ /* Program EMIF0 CFG Registers */
+ phyc.reg = DDR2_EMIF_READ_LATENCY;
+ phyc.reg_sh = DDR2_EMIF_READ_LATENCY;
+ phyc.reg2 = DDR2_EMIF_READ_LATENCY;
- tmg.time1 = EMIF_TIM1;
- tmg.time1_sh = EMIF_TIM1;
- tmg.time2 = EMIF_TIM2;
- tmg.time2_sh = EMIF_TIM2;
- tmg.time3 = EMIF_TIM3;
- tmg.time3_sh = EMIF_TIM3;
+ tmg.time1 = DDR2_EMIF_TIM1;
+ tmg.time1_sh = DDR2_EMIF_TIM1;
+ tmg.time2 = DDR2_EMIF_TIM2;
+ tmg.time2_sh = DDR2_EMIF_TIM2;
+ tmg.time3 = DDR2_EMIF_TIM3;
+ tmg.time3_sh = DDR2_EMIF_TIM3;
- cfg.sdrcr = EMIF_SDCFG;
- cfg.sdrcr2 = EMIF_SDCFG;
- cfg.refresh = EMIF_SDREF;
- cfg.refresh_sh = EMIF_SDREF;
+ cfg.sdrcr = DDR2_EMIF_SDCFG;
+ cfg.sdrcr2 = DDR2_EMIF_SDCFG;
+ cfg.refresh = DDR2_EMIF_SDREF;
+ cfg.refresh_sh = DDR2_EMIF_SDREF;
/* Program EMIF instance */
ret = config_ddr_phy(&phyc);
@@ -159,14 +159,14 @@
config_ddr_data(0, &ddr2_data);
config_ddr_data(1, &ddr2_data);
- writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
- writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
+ writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
+ writel(DDR2_PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
- ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
- ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
- ioctrl.data1ctl = DDR_IOCTRL_VALUE;
- ioctrl.data2ctl = DDR_IOCTRL_VALUE;
+ ioctrl.cmd1ctl = DDR2_IOCTRL_VALUE;
+ ioctrl.cmd2ctl = DDR2_IOCTRL_VALUE;
+ ioctrl.cmd3ctl = DDR2_IOCTRL_VALUE;
+ ioctrl.data1ctl = DDR2_IOCTRL_VALUE;
+ ioctrl.data2ctl = DDR2_IOCTRL_VALUE;
config_io_ctrl(&ioctrl);
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 842e45f..b4735ba 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -22,38 +22,30 @@
#include <asm/arch/hardware.h>
/* AM335X EMIF Register values */
-#define EMIF_SDMGT 0x80000000
-#define EMIF_SDRAM 0x00004650
-#define EMIF_PHYCFG 0x2
-#define DDR_PHY_RESET (0x1 << 10)
-#define DDR_FUNCTIONAL_MODE_EN 0x1
-#define DDR_PHY_READY (0x1 << 2)
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
-#define VTP_CTRL_LOCK_EN (0x1 << 4)
#define VTP_CTRL_START_EN (0x1)
-#define DDR2_RATIO 0x80
#define CMD_FORCE 0x00
#define CMD_DELAY 0x00
+#define PHY_DLL_LOCK_DIFF 0x0
-#define EMIF_READ_LATENCY 0x05
-#define EMIF_TIM1 0x0666B3D6
-#define EMIF_TIM2 0x143731DA
-#define EMIF_TIM3 0x00000347
-#define EMIF_SDCFG 0x43805332
-#define EMIF_SDREF 0x0000081a
+#define DDR2_EMIF_READ_LATENCY 0x05
+#define DDR2_EMIF_TIM1 0x0666B3D6
+#define DDR2_EMIF_TIM2 0x143731DA
+#define DDR2_EMIF_TIM3 0x00000347
+#define DDR2_EMIF_SDCFG 0x43805332
+#define DDR2_EMIF_SDREF 0x0000081a
#define DDR2_DLL_LOCK_DIFF 0x0
-#define DDR2_RD_DQS 0x12
-#define DDR2_PHY_FIFO_WE 0x80
-
+#define DDR2_RATIO 0x80
#define DDR2_INVERT_CLKOUT 0x00
+#define DDR2_RD_DQS 0x12
#define DDR2_WR_DQS 0x00
#define DDR2_PHY_WRLVL 0x00
#define DDR2_PHY_GATELVL 0x00
#define DDR2_PHY_WR_DATA 0x40
-#define PHY_RANK0_DELAY 0x01
-#define PHY_DLL_LOCK_DIFF 0x0
-#define DDR_IOCTRL_VALUE 0x18B
+#define DDR2_PHY_FIFO_WE 0x80
+#define DDR2_PHY_RANK0_DELAY 0x1
+#define DDR2_IOCTRL_VALUE 0x18B
/**
* Encapsulates DDR PHY control and corresponding shadow registers.