tree 837d6be997c2da0a76b1c7d49cbebe5244b7168f
parent f917713bf763d09afafe9ceebf7240e2218658bb
author Dinesh Maniyam <dinesh.maniyam@intel.com> 1740586695 +0800
committer Michael Trimarchi <michael@amarulasolutions.com> 1742031300 +0100

dt: nand: add cadence nand dt-bindings

The Cadence NAND is a configurable mtd raw block which
supports multiple options for chipsets, clocking and reset structure, and
feature list.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>