board/BuR/zynq: initial commit
This commit adds support for the brcp1, brsmarc2, brcp150 and brcp170
boards. This boards are based on the Xilinx Zynq SoC.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20250404072819.69642-5-bernhard.messerklinger@br-automation.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 57d3dd9..bcf3f4b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -303,6 +303,13 @@
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
+dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
+ zynq-brcp1_2r.dtb \
+ zynq-brcp1_1r.dtb \
+ zynq-brcp1_1r_switch.dtb \
+ zynq-brsmarc2.dtb \
+ zynq-brcp150.dtb \
+ zynq-brcp170.dtb
zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
diff --git a/arch/arm/dts/zynq-binman-brcp1.dtsi b/arch/arm/dts/zynq-binman-brcp1.dtsi
new file mode 100644
index 0000000..3cc8ee8
--- /dev/null
+++ b/arch/arm/dts/zynq-binman-brcp1.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 B&R Industrial Automation GmbH
+ */
+
+ #include <config.h>
+
+/ {
+ binman {
+ bootph-all;
+ filename = "flash.bin";
+ pad-byte = <0xff>;
+ align-size = <16>;
+ align = <16>;
+
+ blob@0 {
+ filename = "spl/boot.bin";
+ offset = <0x0>;
+ };
+
+ fit {
+ description = "U-Boot BR Zynq boards";
+ offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
+
+ images {
+ uboot {
+ description = "U-Boot BR Zynq";
+ type = "firmware";
+ os = "u-boot";
+ arch = "arm";
+ compression = "none";
+ load = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
+ };
+ };
+
+ fdt-0 {
+ description = "DTB BR Zynq";
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ u-boot-dtb {
+ };
+ };
+ };
+
+ configurations {
+ default = "conf-0";
+
+ conf-0 {
+ description = "BR Zynq";
+ firmware = "uboot";
+ fdt = "fdt-0";
+ };
+ };
+ };
+
+ blob-ext@0 {
+ filename = "blobs/cfg.img";
+ offset = <0xC0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@5 {
+ filename = "blobs/cfg_opt.img";
+ offset = <0xD0000>;
+ size = <0x10000>;
+ optional;
+ };
+
+ blob-ext@1 {
+ bootph-all;
+ filename = "blobs/bitstream.bit";
+ offset = <0x100000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@4 {
+ bootph-all;
+ filename = "blobs/bitstream_update.bit";
+ offset = <0x400000>;
+ size = <0x200000>;
+ optional;
+ };
+
+ blob-ext@2 {
+ filename = "blobs/bootar.itb";
+ offset = <0x900000>;
+ size = <0x600000>;
+ optional;
+ };
+
+ blob-ext@3 {
+ filename = "blobs/dtb.bin";
+ offset = <0xF00000>;
+ size = <0x100000>;
+ optional;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1.dtsi b/arch/arm/dts/zynq-brcp1.dtsi
new file mode 100644
index 0000000..ebaf42d
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP1 CPU";
+ compatible = "br,cp1",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+
+ pmic0: da9062@58 {
+ compatible = "dlg,da9062";
+ reg = <0x58>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp150-u-boot.dtsi b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
new file mode 100644
index 0000000..1bfd5f2
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
+
+&rs232_en {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp150.dts b/arch/arm/dts/zynq-brcp150.dts
new file mode 100644
index 0000000..1b22d37
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp150.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP150 CPU";
+ compatible = "br,cp150",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* Put this pin active high to enable RS232 debug serial */
+ rs232_en: rs232_enable {
+ compatible = "br,rs232-en";
+ pin = <&gpio0 52 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_green {
+ label = "USER1_GREEN";
+ gpios = <&ledgpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user1_red {
+ label = "USER1_RED";
+ gpios = <&ledgpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_green {
+ label = "USER2_GREEN";
+ gpios = <&ledgpio 14 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ user2_red {
+ label = "USER2_RED";
+ gpios = <&ledgpio 15 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "mii";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: emio-phy@2 {
+ reg = <2>;
+ max-speed = <100>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <16>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp170-u-boot.dtsi b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
new file mode 100644
index 0000000..ceea610
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170-u-boot.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp170.dts b/arch/arm/dts/zynq-brcp170.dts
new file mode 100644
index 0000000..eee19ce
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp170.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRCP170 CPU";
+ compatible = "br,cp170",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_red {
+ label = "RDY_F_RED";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_green {
+ label = "S_E_GREEN";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ se_red {
+ label = "S_E_RED";
+ gpios = <&ledgpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ eth_se_green {
+ label = "ETH_S_E_GREEN";
+ gpios = <&ledgpio 7 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ max-speed = <100>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ ledgpio: max7320@58 { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x58>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};
+
+&gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
new file mode 100644
index 0000000..58c4558
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r.dts b/arch/arm/dts/zynq-brcp1_1r.dts
new file mode 100644
index 0000000..fd7ae55
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
new file mode 120000
index 0000000..5a31a05
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_1r_switch.dts b/arch/arm/dts/zynq-brcp1_1r_switch.dts
new file mode 100644
index 0000000..a68d530
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_1r_switch.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "gmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+};
+
+/* Since the gem0 clock is configured EMIO this dummy entry is needed */
+&clkc {
+ clocks = <&clkc 16>;
+ clock-names = "gem0_emio_clk";
+};
diff --git a/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
new file mode 120000
index 0000000..5a31a05
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r-u-boot.dtsi
@@ -0,0 +1 @@
+zynq-brcp1_1r-u-boot.dtsi
\ No newline at end of file
diff --git a/arch/arm/dts/zynq-brcp1_2r.dts b/arch/arm/dts/zynq-brcp1_2r.dts
new file mode 100644
index 0000000..353d8a1
--- /dev/null
+++ b/arch/arm/dts/zynq-brcp1_2r.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+#include "zynq-brcp1.dtsi"
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <7>;
+ ti,tx-internal-delay = <7>;
+ ti,fifo-depth = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
new file mode 100644
index 0000000..58c4558
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2-u-boot.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+#include "zynq-binman-brcp1.dtsi"
+
+&i2c0 {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&qspi {
+ bootph-all;
+};
+
+&spi_flash {
+ bootph-all;
+};
+
+&gpio0 {
+ bootph-all;
+};
+
+&brd_rst {
+ bootph-all;
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 0000000..32f873d
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 B&R Industrial Automation GmbH
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "BRSMARC2 CPU";
+ compatible = "br,smarc2",
+ "xlnx,zynq-7000";
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ can0 = &can0;
+ can1 = &can1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ usb_phy0: phy0 {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ brd_rst: board_reset {
+ compatible = "br,board-reset";
+ pin = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ plk_se_green {
+ label = "PLK_S_E_GREEN";
+ gpios = <&ledgpio 0 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ plk_se_red {
+ label = "PLK_S_E_RED";
+ gpios = <&ledgpio 1 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ rdy_f_yellow {
+ label = "RDY_F_YELLOW";
+ gpios = <&ledgpio 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_green {
+ label = "R_E_GREEN";
+ gpios = <&ledgpio 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ re_red {
+ label = "R_E_RED";
+ gpios = <&ledgpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+
+ ethernet_phy0: ethernet-phy@1 {
+ ti,ledcr = <0x0480>;
+ ti,rgmii-rxclk-shift;
+ reg = <1>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy1>;
+ mac-address = [ 00 00 00 00 00 00 ];
+
+ ethernet_phy1: ethernet-phy@3{
+ ti,ledcr = <0x0480>;
+ reg = <3>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ resetc: rststm@60 { /* reset controller */
+ compatible = "bur,rststm";
+ reg = <0x60>;
+ hit-gpios = <&gpio0 84 GPIO_ACTIVE_HIGH>;
+ cooling-min-state = <0>;
+ cooling-max-state = <1>; /* reset gets fired */
+ #cooling-cells = <2>; /* min followed by max */
+ };
+
+ ledgpio: max7320@5d { /* board LED */
+ status = "okay";
+ compatible = "maxim,max7320";
+ reg = <0x5d>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ ngpios = <8>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&sdhci0 {
+ status = "okay";
+ max-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+ spi-max-frequency = <100000000>;
+
+ spi_flash: spiflash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor", "spi-flash", "s25fl256s1";
+ spi-max-frequency = <100000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ usb-phy = <&usb_phy0>;
+};