tree d65bba782032e9789ca6f55e1a2744094272ce94
parent c2a441cbbe85d81d5104a349bb8fadd8879348c3
author Michael Walle <mwalle@kernel.org> 1715633768 +0200
committer Andre Przywara <andre.przywara@arm.com> 1721078296 +0100

clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC

Add the clock gate registers as well as the reset register bits for the
EMAC and EPHY for the V3s. These are needed by the sun8i network driver.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>