| commit | f3471e1a4d886f597577195ac2e70f7a58364dbf | [log] [tgz] |
|---|---|---|
| author | Paul Barker <paul.barker.ct@bp.renesas.com> | Fri Nov 01 14:20:16 2024 +0000 |
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | Sun Nov 10 19:36:54 2024 +0100 |
| tree | 1abc104b692dd5cd950413cded949897c56ffc59 | |
| parent | e26e83f66cb84b48c110cd2e80808b9812ac657f [diff] |
arm: renesas: Fix RZ/G2L GICR base address
When support for the Renesas RZ/G2L SoC was added, the GICR base address
for CPU1 was accidentally used. We should instead supply the GICR base
address for CPU0 so that interrupts are correctly configured for the
CPU core that U-Boot is actually using.
Fixes: 387d4275ab0e ("arm: rmobile: Add basic RZ/G2L family support")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>