ARM: tegra: Tegra20 pinmux cleanup
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.
The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.
All affected code is updated to match.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index 603c024..b5d561b 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -208,9 +208,9 @@
* SPI pins on Tegra20 are muxed - change pinmux later due to UART
* issue.
*/
- pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
- pinmux_tristate_disable(PINGRP_LSPI);
- pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
+ pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
+ pinmux_tristate_disable(PMUX_PINGRP_LSPI);
+ pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
return 0;
}
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index c047e6e..57cb007 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -229,8 +229,8 @@
break;
case STAGE_PWM:
/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
- pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
break;