tree 30d9094bd93816813661749537788a93895f1b68
parent 00c55c6f0f674c0bc3fade772de3c79777d84633
author Andre Przywara <andre.przywara@arm.com> 1740569831 +0000
committer Andre Przywara <andre.przywara@arm.com> 1743035195 +0000

sunxi: mmc: Fix T113-s3 MMC clock divider

On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
But we have still the hidden divisor of 2 in the MMC mod clock, so
need to explicitly compensate for that on those SoCs.

This leads to the actually programmed clock rate to be double compared
to before, which increases the MMC performance on those SoCs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>