x86: apl: Add core init for the SoC
Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
index a4c9c96..d37f91d 100644
--- a/arch/x86/cpu/apollolake/cpu.c
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -13,6 +13,9 @@
#include <asm/cpu_x86.h>
#include <asm/intel_acpi.h>
#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/iomap.h>
#include <dm/acpi.h>
#define CSTATE_RES(address_space, width, offset, address) \
@@ -86,6 +89,86 @@
return 0;
}
+static void update_fixed_mtrrs(void)
+{
+ native_write_msr(MTRR_FIX_64K_00000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_16K_80000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_E0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_E8000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_F0000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ native_write_msr(MTRR_FIX_4K_F8000_MSR,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+}
+
+static void setup_core_msrs(void)
+{
+ wrmsrl(MSR_PMG_CST_CONFIG_CONTROL,
+ PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK |
+ IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK);
+ /* Power Management I/O base address for I/O trapping to C-states */
+ wrmsrl(MSR_PMG_IO_CAPTURE_ADR, ACPI_PMIO_CST_REG |
+ (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16));
+ /* Disable C1E */
+ msr_clrsetbits_64(MSR_POWER_CTL, 0x2, 0);
+ /* Disable support for MONITOR and MWAIT instructions */
+ msr_clrsetbits_64(MSR_IA32_MISC_ENABLE, MISC_ENABLE_MWAIT, 0);
+ /*
+ * Enable and Lock the Advanced Encryption Standard (AES-NI)
+ * feature register
+ */
+ msr_clrsetbits_64(MSR_FEATURE_CONFIG, FEATURE_CONFIG_RESERVED_MASK,
+ FEATURE_CONFIG_LOCK);
+
+ update_fixed_mtrrs();
+}
+
+static int soc_core_init(void)
+{
+ struct udevice *pmc;
+ int ret;
+
+ /* Clear out pending MCEs */
+ cpu_mca_configure();
+
+ /* Set core MSRs */
+ setup_core_msrs();
+ /*
+ * Enable ACPI PM timer emulation, which also lets microcode know
+ * location of ACPI_BASE_ADDRESS. This also enables other features
+ * implemented in microcode.
+ */
+ ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
+ if (ret)
+ return log_msg_ret("PMC", ret);
+ enable_pm_timer_emulation(pmc);
+
+ return 0;
+}
+
+static int cpu_apl_probe(struct udevice *dev)
+{
+ if (gd->flags & GD_FLG_RELOC) {
+ int ret;
+
+ ret = soc_core_init();
+ if (ret)
+ return log_ret(ret);
+ }
+
+ return 0;
+}
+
struct acpi_ops apl_cpu_acpi_ops = {
.fill_ssdt = acpi_cpu_fill_ssdt,
};
@@ -107,6 +190,7 @@
.id = UCLASS_CPU,
.of_match = cpu_x86_apl_ids,
.bind = cpu_x86_bind,
+ .probe = cpu_apl_probe,
.ops = &cpu_x86_apl_ops,
ACPI_OPS_PTR(&apl_cpu_acpi_ops)
.flags = DM_FLAG_PRE_RELOC,
diff --git a/arch/x86/cpu/apollolake/cpu_common.c b/arch/x86/cpu/apollolake/cpu_common.c
index ba6bda3..63f6999 100644
--- a/arch/x86/cpu/apollolake/cpu_common.c
+++ b/arch/x86/cpu/apollolake/cpu_common.c
@@ -4,8 +4,13 @@
*/
#include <common.h>
+#include <dm.h>
+#include <log.h>
#include <asm/cpu_common.h>
#include <asm/msr.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/iomap.h>
+#include <power/acpi_pmc.h>
void cpu_flush_l1d_to_l2(void)
{
@@ -15,3 +20,23 @@
msr.lo |= FLUSH_DL1_L2;
msr_write(MSR_POWER_MISC, msr);
}
+
+void enable_pm_timer_emulation(const struct udevice *pmc)
+{
+ struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
+ msr_t msr;
+
+ /*
+ * The derived frequency is calculated as follows:
+ * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
+ *
+ * Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
+ * used.
+ */
+ msr.hi = (3579545ULL << 32) / CTC_FREQ;
+
+ /* Set PM1 timer IO port and enable */
+ msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
+ debug("PM timer %x %x\n", msr.hi, msr.lo);
+ msr_write(MSR_EMULATE_PM_TIMER, msr);
+}
diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c
index 9f32f2e..fafe4db 100644
--- a/arch/x86/cpu/apollolake/cpu_spl.c
+++ b/arch/x86/cpu/apollolake/cpu_spl.c
@@ -114,26 +114,6 @@
return 0;
}
-static void enable_pm_timer_emulation(struct udevice *pmc)
-{
- struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
- msr_t msr;
-
- /*
- * The derived frequency is calculated as follows:
- * (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
- *
- * Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
- * used.
- */
- msr.hi = (3579545ULL << 32) / CTC_FREQ;
-
- /* Set PM1 timer IO port and enable */
- msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
- debug("PM timer %x %x\n", msr.hi, msr.lo);
- msr_write(MSR_EMULATE_PM_TIMER, msr);
-}
-
static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
{
uint base;