x86: quark: Implement PIRQ routing
Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index c0a937f..a3b564e 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -6,3 +6,4 @@
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_GENERATE_PIRQ_TABLE=y