OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
In function get_osc_clk_speed(), do not change/ update
the divider for SYS_CLK as it can has cascading effect
on the other derived clocks.
Sudden change in divider value can lead to inconsistent
behavior in the system - often leading to crashes.
The problem was found when working with OMAP3EVM using
DM3730 processor card.
The patch has been tested with OMAP3530 on OMAP3EVM as
well
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Hiremath Vaibhav <hvaibhav@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index 174c453..6330c9e 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -40,7 +40,7 @@
*****************************************************************************/
u32 get_osc_clk_speed(void)
{
- u32 start, cstart, cend, cdiff, val;
+ u32 start, cstart, cend, cdiff, cdiv, val;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
struct prm *prm_base = (struct prm *)PRM_BASE;
struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
@@ -48,9 +48,15 @@
val = readl(&prm_base->clksrc_ctrl);
- /* If SYS_CLK is being divided by 2, remove for now */
- val = (val & (~SYSCLKDIV_2)) | SYSCLKDIV_1;
- writel(val, &prm_base->clksrc_ctrl);
+ if (val & SYSCLKDIV_2)
+ cdiv = 2;
+ else if (val & SYSCLKDIV_1)
+ cdiv = 1;
+ else
+ /*
+ * Should never reach here! (Assume divider as 1)
+ */
+ cdiv = 1;
/* enable timer2 */
val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
@@ -61,6 +67,7 @@
/* Enable I and F Clocks for GPT1 */
val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
writel(val, &prcm_base->iclken_wkup);
+
val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
writel(val, &prcm_base->fclken_wkup);
@@ -83,6 +90,11 @@
cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
cdiff = cend - cstart; /* get elapsed ticks */
+ if (cdiv == 2)
+ {
+ cdiff *= 2;
+ }
+
/* based on number of ticks assign speed */
if (cdiff > 19000)
return S38_4M;