* Patch by Josef Wagner, 12 Mar 2003:
- 16/32 MB and 50/80 MHz support with auto-detection for IP860
- ETH05 and BEDBUG support for CU824
- added support for MicroSys CPC45
- new BOOTROM/FLASH0 and DOC base for PM826
* Patch by Robert Schwebel, 12 Mar 2003:
Fix the chpart command on innokom board
* Name cleanup:
mv include/asm-i386/ppcboot-i386.h include/asm-i386/u-boot-i386.h
s/PPCBoot/U-Boot/ in some files
s/pImage/uImage/ in some files
* Patch by Detlev Zundel, 15 Jan 2003:
Fix '' command line quoting
* Patch by The LEOX team, 19 Jan 2003:
- add support for the ELPT860 board
- add support for Dallas ds164x RTC
diff --git a/include/asm-i386/ppcboot-i386.h b/include/asm-i386/u-boot-i386.h
similarity index 95%
rename from include/asm-i386/ppcboot-i386.h
rename to include/asm-i386/u-boot-i386.h
index 704526e..6e5e059 100644
--- a/include/asm-i386/ppcboot-i386.h
+++ b/include/asm-i386/u-boot-i386.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef _PPCBOOT_I386_H_
-#define _PPCBOOT_I386_H_ 1
+#ifndef _U_BOOT_I386_H_
+#define _U_BOOT_I386_H_ 1
/* for the following variables, see start.S */
extern ulong i386boot_start; /* code start (in flash) */
@@ -50,4 +50,4 @@
int dram_init (void);
-#endif /* _PPCBOOT_I386_H_ */
+#endif /* _U_BOOT_I386_H_ */
diff --git a/include/common.h b/include/common.h
index bce0132..ac2a57d 100644
--- a/include/common.h
+++ b/include/common.h
@@ -149,7 +149,7 @@
# include <asm/u-boot-arm.h> /* ARM version to be fixed! */
#endif /* CONFIG_ARM */
#ifdef CONFIG_I386 /* x86 version to be fixed! */
-# include <asm/ppcboot-i386.h>
+# include <asm/u-boot-i386.h>
#endif /* CONFIG_I386 */
void pci_init (void);
diff --git a/include/commproc.h b/include/commproc.h
index 159c294..5ff82b7 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -595,6 +595,32 @@
#endif /* CONFIG_PCU_E, CONFIG_CCM */
+/*** ELPT860 *********************************************************/
+
+#ifdef CONFIG_ELPT860
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+# define PROFF_ENET PROFF_SCC1
+# define CPM_CR_ENET CPM_CR_CH_SCC1
+# define SCC_ENET 0
+
+# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
+# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
+# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
+# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
+
+# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
+# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
+# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
+ * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+# define SICR_ENET_MASK ((uint)0x000000FF)
+# define SICR_ENET_CLKRT ((uint)0x00000025)
+#endif /* CONFIG_ELPT860 */
+
/*** ESTEEM 192E **************************************************/
#ifdef CONFIG_ESTEEM192E
/* ESTEEM192E
diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
new file mode 100644
index 0000000..ed843d4
--- /dev/null
+++ b/include/configs/CPC45.h
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *
+ * Configuration settings for the CPC45 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC824X 1
+#define CONFIG_MPC8245 1
+#define CONFIG_CPC45 1
+
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 9600
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PCI | \
+ 0 /* CFG_CMD_DATE */ )
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
+ */
+#include <cmd_confdefs.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+
+#if 1
+#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
+#endif
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* Print Buffer Size
+ */
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+
+#define CFG_SDRAM_BASE 0x00000000
+
+#if defined(CONFIG_BOOT_ROM)
+#define CFG_FLASH_BASE 0xFF000000
+#else
+#define CFG_FLASH_BASE 0xFF800000
+#endif
+
+#define CFG_RESET_ADDRESS 0xFFF00100
+
+#define CFG_EUMB_ADDR 0xFCE00000
+
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
+#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
+
+ /* Maximum amount of RAM.
+ */
+#define CFG_MAX_RAM_SIZE 0x10000000
+
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#undef CFG_RAMBOOT
+#else
+#define CFG_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+ /* Size in bytes reserved for initial data
+ */
+#define CFG_GBL_DATA_SIZE 128
+
+#define CFG_INIT_RAM_ADDR 0x40000000
+#define CFG_INIT_RAM_END 0x1000
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+
+#define CFG_NS16550_REG_SIZE 1
+
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_NS16550_COM1 (CFG_EUMB_ADDR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_EUMB_ADDR + 0x4600)
+#define DUART_DCR (CFG_EUMB_ADDR + 0x4511)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ 33000000
+#define CFG_HZ 1000
+/*
+ * SDRAM Configuration Settings
+ * Please note: currently only 64 and 128 MB SDRAM size supported
+ * set CFG_SDRAM_SIZE to 64 or 128
+ * Memory configuration using SPD information stored on the SODIMMs
+ * not yet supported.
+ */
+
+#define CFG_SDRAM_SIZE 64 /* SDRAM size -- 64 or 128 MB supported */
+
+ /* Bit-field values for MCCR1.
+ */
+#define CFG_ROMNAL 0
+#define CFG_ROMFAL 7
+
+#if (CFG_SDRAM_SIZE == 64) /* 64 MB */
+#define CFG_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
+#elif (CFG_SDRAM_SIZE == 128) /* 128 MB */
+#define CFG_BANK0_ROW 2 /* SDRAM bank 7-0 row address */
+#else
+# error "SDRAM size not supported"
+#endif
+#define CFG_BANK1_ROW 0
+#define CFG_BANK2_ROW 0
+#define CFG_BANK3_ROW 0
+#define CFG_BANK4_ROW 0
+#define CFG_BANK5_ROW 0
+#define CFG_BANK6_ROW 0
+#define CFG_BANK7_ROW 0
+
+ /* Bit-field values for MCCR2.
+ */
+#define CFG_REFINT 430 /* Refresh interval */
+
+ /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CFG_BSTOPRE 192
+
+ /* Bit-field values for MCCR3.
+ */
+#define CFG_REFREC 2 /* Refresh to activate interval */
+#define CFG_RDLAT 3 /* Data latancy from read command */
+
+ /* Bit-field values for MCCR4.
+ */
+#define CFG_PRETOACT 2 /* Precharge to activate interval */
+#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
+#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
+#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
+#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
+#define CFG_ACTORW 2
+#define CFG_REGISTERD_TYPE_BUFFER 1
+#define CFG_EXTROM 1
+#define CFG_REGDIMM 0
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CFG_BANK0_START 0x00000000
+#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
+#define CFG_BANK0_ENABLE 1
+#define CFG_BANK1_START 0x3ff00000
+#define CFG_BANK1_END 0x3fffffff
+#define CFG_BANK1_ENABLE 0
+#define CFG_BANK2_START 0x3ff00000
+#define CFG_BANK2_END 0x3fffffff
+#define CFG_BANK2_ENABLE 0
+#define CFG_BANK3_START 0x3ff00000
+#define CFG_BANK3_END 0x3fffffff
+#define CFG_BANK3_ENABLE 0
+#define CFG_BANK4_START 0x3ff00000
+#define CFG_BANK4_END 0x3fffffff
+#define CFG_BANK4_ENABLE 0
+#define CFG_BANK5_START 0x3ff00000
+#define CFG_BANK5_END 0x3fffffff
+#define CFG_BANK5_ENABLE 0
+#define CFG_BANK6_START 0x3ff00000
+#define CFG_BANK6_END 0x3fffffff
+#define CFG_BANK6_ENABLE 0
+#define CFG_BANK7_START 0x3ff00000
+#define CFG_BANK7_END 0x3fffffff
+#define CFG_BANK7_ENABLE 0
+
+#define CFG_ODCR 0xff
+
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CFG_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
+#define CFG_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
+#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+ /* Warining: environment is not EMBEDDED in the ppcboot code.
+ * It's stored in flash separately.
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x7C0000)
+#define CFG_ENV_SIZE 0x4000 /* Size of the Environment */
+#define CFG_ENV_OFFSET 0 /* starting right at the beginning */
+#define CFG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+#define SRAM_BASE 0x80000000 /* SRAM base address */
+#define SRAM_END 0x801FFFFF
+
+/*---------------------------------------------------------------------*/
+/* CPC45 Memory Map */
+/*---------------------------------------------------------------------*/
+#define SRAM_BASE 0x80000000 /* SRAM base address */
+#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
+#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
+#define BCSR_BASE 0x80600000 /* board control / status registers */
+#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
+#define PCMCIA_MEM_BASE 0x81000000 /* PCMCIA memory window base */
+#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
+
+
+/*---------------------------------------------------------------------*/
+/* CPC45 Control/Status Registers */
+/*---------------------------------------------------------------------*/
+#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
+#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
+#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
+#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
+#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
+#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
+#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
+#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
+
+/* IRQ_ENA_1 bit definitions */
+#define I_ENA_1_IERA 0x80 /* INTA enable */
+#define I_ENA_1_IERB 0x40 /* INTB enable */
+#define I_ENA_1_IERC 0x20 /* INTC enable */
+#define I_ENA_1_IERD 0x10 /* INTD enable */
+
+/* IRQ_STAT_1 bit definitions */
+#define I_STAT_1_INTA 0x80 /* INTA status */
+#define I_STAT_1_INTB 0x40 /* INTB status */
+#define I_STAT_1_INTC 0x20 /* INTC status */
+#define I_STAT_1_INTD 0x10 /* INTD status */
+
+/* IRQ_ENA_2 bit definitions */
+#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
+#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
+#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
+#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
+#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
+#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
+#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
+#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
+
+/* IRQ_STAT_2 bit definitions */
+#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
+#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
+#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
+#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
+#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
+#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
+#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
+#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
+
+/* BOARD_CTRL bit definitions */
+#define USER_LEDS 2 /* 2 user LEDs */
+
+#if (USER_LEDS == 4)
+#define B_CTRL_WRSE 0x80
+#define B_CTRL_KRSE 0x40
+#define B_CTRL_FWRE 0x20 /* Flash write enable */
+#define B_CTRL_FWPT 0x10 /* Flash write protect */
+#define B_CTRL_LED3 0x08 /* LED 3 control */
+#define B_CTRL_LED2 0x04 /* LED 2 control */
+#define B_CTRL_LED1 0x02 /* LED 1 control */
+#define B_CTRL_LED0 0x01 /* LED 0 control */
+#else
+#define B_CTRL_WRSE 0x80
+#define B_CTRL_KRSE 0x40
+#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
+#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
+#define B_CTRL_LED1 0x08 /* LED 1 control */
+#define B_CTRL_LED0 0x04 /* LED 0 control */
+#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
+#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
+#endif
+
+/* BOARD_STAT bit definitions */
+#define B_STAT_WDGE 0x80
+#define B_STAT_WDGS 0x40
+#define B_STAT_WRST 0x20
+#define B_STAT_KRST 0x10
+#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
+#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
+#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
+#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
+
+/*---------------------------------------------------------------------*/
+/* Display addresses */
+/*---------------------------------------------------------------------*/
+#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
+#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
+#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
+
+#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
+#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
+
+#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
+#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
+#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
+#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
+#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
+#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
+#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
+#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI /* Multi ethernet cards support */
+
+#define CONFIG_EEPRO100
+
+#define PCI_ENET0_IOADDR 0x00104000
+#define PCI_ENET0_MEMADDR 0x82000000
+#define PCI_PLX9030_MEMADDR 0x82100000
+#endif /* __CONFIG_H */
diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h
index ae8525f..9712d47 100644
--- a/include/configs/CPU86.h
+++ b/include/configs/CPU86.h
@@ -171,7 +171,7 @@
CFG_CMD_EEPROM | \
CFG_CMD_DATE | \
CFG_CMD_I2C | \
- CFG_CMD_DOC)
+ CFG_CMD_DOC )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -329,8 +329,8 @@
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_ENV_OFFSET 0
-#define CFG_ENV_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (2048 - 512)
#endif
/*
diff --git a/include/configs/CU824.h b/include/configs/CU824.h
index ed38ef6..40ba25a 100644
--- a/include/configs/CU824.h
+++ b/include/configs/CU824.h
@@ -60,9 +60,10 @@
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_BEDBUG | \
CFG_CMD_DHCP | \
CFG_CMD_PCI | \
- 0/* CFG_CMD_DATE */ )
+ 0 /* CFG_CMD_DATE */ )
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
@@ -302,4 +303,7 @@
#define CFG_ETH_DEV_FN 0x7800
#define CFG_ETH_IOBASE 0x00104000
+#define CONFIG_EEPRO100
+#define PCI_ENET0_IOADDR 0x00104000
+#define PCI_ENET0_MEMADDR 0x80000000
#endif /* __CONFIG_H */
diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h
new file mode 100644
index 0000000..e9561b9
--- /dev/null
+++ b/include/configs/ELPT860.h
@@ -0,0 +1,390 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+** for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+** This program is free software; you can redistribute it and/or
+** modify it under the terms of the GNU General Public License as
+** published by the Free Software Foundation; either version 2 of
+** the License, or (at your option) any later version.
+**
+** This program is distributed in the hope that it will be useful,
+** but WITHOUT ANY WARRANTY; without even the implied warranty of
+** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+** GNU General Public License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with this program; if not, write to the Free Software
+** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+** MA 02111-1307 USA
+**
+**=====================================================================
+*/
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860 1 /* It's a MPC860, in fact a 860T CPU */
+#define CONFIG_MPC860T 1
+#define CONFIG_ELPT860 1 /* ...on a LEOX's ELPT860 CPU board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_CLOCKS_IN_MHZ 1 /* Clock passed to Linux (<2.4.5) in MHz */
+#define CONFIG_8xx_GCLK_FREQ 50000000 /* MPC860T runs at 50MHz */
+
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
+
+/* BOOT arguments */
+#define CONFIG_PREBOOT \
+ "echo;" \
+ "echo Type \"run nfsboot\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "rootargs=setenv rootpath /tftp/$(ipaddr)\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$(serverip):$(rootpath)\0" \
+ "addip=setenv bootargs $(bootargs) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+ ":$(hostname):eth0:off panic=1\0" \
+ "ramboot=tftp 400000 /home/paugaml/pMulti;" \
+ "run ramargs;bootm\0" \
+ "nfsboot=tftp 400000 /home/paugaml/uImage;" \
+ "run rootargs;run nfsargs;run addip;bootm\0" \
+ ""
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
+#undef CONFIG_RTC_MPC8xx /* internal RTC MPC8xx unused */
+#define CONFIG_RTC_DS164x 1 /* RTC is a Dallas DS1646 */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Environment Variables and Storages
+ */
+#define CONFIG_ENV_OVERWRITE 1 /* Allow Overwrite of serial# & ethaddr */
+
+#undef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
+#undef CFG_ENV_IS_IN_EEPROM /* Environment is in I2C EEPROM */
+#define CFG_ENV_IS_IN_FLASH 1 /* Environment is in FLASH */
+
+#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_ETHADDR 00:01:77:00:60:40
+#define CONFIG_IPADDR 192.168.0.30
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_SERVERIP 192.168.0.1
+#define CONFIG_GATEWAYIP 192.168.0.1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
+#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x02000000
+#define CFG_NVRAM_BASE 0x03000000
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# if defined(DEBUG)
+# define CFG_MONITOR_LEN (320 << 10) /* Reserve 320 kB for Monitor */
+# else
+# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+# endif
+#else
+# if defined(DEBUG)
+# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+# else
+# define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+# endif
+#endif
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
+# define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+#endif
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_NVRAM_BASE_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
+#define CFG_NVRAM_SIZE ((128*1024)-8) /* clock regs resident in the */
+ /* 8 top NVRAM locations */
+
+#if defined(CFG_ENV_IS_IN_NVRAM)
+# define CFG_ENV_ADDR CFG_NVRAM_BASE /* Base address of NVRAM area */
+# define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+# define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CFG_SIUMCR (SIUMCR_DBGC11)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
+ * enabled
+ */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+#define CFG_SCCR (SCCR_TBS | \
+ SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
+ SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
+ *-----------------------------------------------------------------------
+ *
+ */
+#ifdef DEBUG
+# define CFG_DER 0xFFE7400F /* Debug Enable Register */
+#else
+# define CFG_DER 0
+#endif
+
+/*
+ * Init Memory Controller:
+ * ~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_PRELIM_OR_AM 0xFF000000 /* 16 MB between each CSx */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0 */
+#define CFG_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
+
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM CFG_SDRAM_BASE /* SDRAM bank #0 */
+#define SDRAM_MAX_SIZE 0x02000000 /* 32 MB MAX for CS1 */
+
+/* SDRAM timing: */
+#define CFG_OR_TIMING_SDRAM 0x00000000
+
+#define CFG_OR1_PRELIM ((2 * CFG_PRELIM_OR_AM) | CFG_OR_TIMING_SDRAM )
+#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2 and OR2 (NVRAM)
+ *
+ */
+#define NVRAM_BASE1_PRELIM CFG_NVRAM_BASE /* NVRAM bank #0 */
+#define NVRAM_MAX_SIZE 0x00020000 /* 128 KB MAX for CS2 */
+
+#define CFG_OR2_PRELIM 0xFFF80160
+#define CFG_BR2_PRELIM ((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
+#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
+#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*-----------------------------------------------------------------------
+ * Internal Definitions
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/IP860.h b/include/configs/IP860.h
index 6fa2d19..d7dce71 100644
--- a/include/configs/IP860.h
+++ b/include/configs/IP860.h
@@ -35,6 +35,7 @@
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_IP860 1 /* ...on a IP860 board */
+#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 9600
@@ -45,10 +46,6 @@
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"
-#define CONFIG_ETHADDR 00:30:bf:01:02:d2
-#define CONFIG_IPADDR 10.0.0.5
-#define CONFIG_SERVERIP 10.0.0.2
-
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
@@ -230,10 +227,13 @@
SIUMCR_DBGC11 | SIUMCR_MLRC10)
/*-----------------------------------------------------------------------
- * Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails
+ * Clock Setting - get clock frequency from Board Revision Register
*-----------------------------------------------------------------------
*/
-#define CONFIG_8xx_GCLK_FREQ 50000000
+#ifndef __ASSEMBLY__
+extern unsigned long ip860_get_clk_freq (void);
+#endif
+#define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq()
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
@@ -430,6 +430,8 @@
unsigned char wd_trigger; /* +1A Watchdog trigger register */
unsigned char reservedD;
unsigned char rmw_req; /* +1C RMW request register */
+ unsigned char reservedE;
+ unsigned char bd_rev; /* +1E Board Revision register */
} ip860_bcsr_t;
#endif /* __ASSEMBLY__ */
diff --git a/include/configs/PM826.h b/include/configs/PM826.h
index b56da69..d95596c 100644
--- a/include/configs/PM826.h
+++ b/include/configs/PM826.h
@@ -158,9 +158,9 @@
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BEDBUG | \
CFG_CMD_DATE | \
+ CFG_CMD_DOC | \
CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_DOC)
+ CFG_CMD_I2C )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -211,11 +211,11 @@
* Flash and Boot ROM mapping
*/
-#define CFG_BOOTROM_BASE 0x60000000
+#define CFG_BOOTROM_BASE 0xFF800000
#define CFG_BOOTROM_SIZE 0x00080000
-#define CFG_FLASH0_BASE 0x40000000
+#define CFG_FLASH0_BASE 0xFF000000
#define CFG_FLASH0_SIZE 0x02000000
-#define CFG_DOC_BASE 0x60000000
+#define CFG_DOC_BASE 0xFF800000
#define CFG_DOC_SIZE 0x00100000
@@ -245,8 +245,8 @@
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_ENV_OFFSET 0
-#define CFG_ENV_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (2048 - 512)
#endif
/*-----------------------------------------------------------------------
diff --git a/include/configs/PN62.h b/include/configs/PN62.h
index 0750116..6c37208 100644
--- a/include/configs/PN62.h
+++ b/include/configs/PN62.h
@@ -70,7 +70,7 @@
"root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip)::$(netmask):pn62:eth0:off;" \
"loadp 100000; bootm"
- /* "tftpboot 100000 pImage; bootm" */
+ /* "tftpboot 100000 uImage; bootm" */
#else
/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
#define CONFIG_BOOTCOMMAND \
diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h
index ad36c95..acfe747 100644
--- a/include/configs/RRvision.h
+++ b/include/configs/RRvision.h
@@ -75,7 +75,7 @@
"setenv filesize;saveenv\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
- "kernel_img=/tftpboot/pImage\0" \
+ "kernel_img=/tftpboot/uImage\0" \
"kernel_load=tftp 200000 $(kernel_img)\0" \
"net_nfs=run kernel_load nfsargs addip addtty;bootm\0" \
"flash_nfs=run nfsargs addip addtty;bootm $(kernel_addr)\0" \
diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h
index bbd5939..9ad1839 100644
--- a/include/configs/SPD823TS.h
+++ b/include/configs/SPD823TS.h
@@ -74,7 +74,7 @@
#define CONFIG_IPADDR 10.0.0.98
#define CONFIG_SERVERIP 10.0.0.1
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "tftp 200000 pImage;bootm 200000"
+#define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
/*----------------------------------------------------------------------*/
/*
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 6836326..cc51ce6 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -71,7 +71,7 @@
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM860L/pImage\0" \
+ "bootfile=/tftpboot/TQM860L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
""
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 71e08ce..60aacfb 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -67,7 +67,7 @@
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM860L/pImage\0" \
+ "bootfile=/tftpboot/TQM860L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
""
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index ac0e28a..37363a2 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -67,7 +67,7 @@
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM860L/pImage\0" \
+ "bootfile=/tftpboot/TQM860L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
""
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 5564b23..0d0b8c3 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -67,7 +67,7 @@
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
- "bootfile=/tftpboot/TQM860L/pImage\0" \
+ "bootfile=/tftpboot/TQM860L/uImage\0" \
"kernel_addr=40040000\0" \
"ramdisk_addr=40100000\0" \
""
diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h
index 66c7935..fa46600 100644
--- a/include/configs/lwmon.h
+++ b/include/configs/lwmon.h
@@ -97,7 +97,7 @@
"bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip add_wdt addfb add_misc;" \
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
- "net_nfs=tftp 100000 /tftpboot/pImage.lwmon;" \
+ "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;" \
"run nfsargs addip add_wdt addfb;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"load=tftp 100000 /tftpboot/u-boot.bin\0" \