| commit | eed60cebfade1fd4ded2924e3820e88bda33404a | [log] [tgz] |
|---|---|---|
| author | Dave Liu <daveliu@freescale.com> | Fri Mar 27 14:32:43 2009 +0800 |
| committer | Wolfgang Denk <wd@denx.de> | Tue Jun 09 22:58:05 2009 +0200 |
| tree | 7ac021abc9b1e6f08dc64de6128868a28cabd175 | |
| parent | 310a9db3ac81c73d28d721713017ded01334761e [diff] |
85xx: Fix the clock adjust of mpc8569mds board Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu <daveliu@freescale.com>