omap3: Configure RAM bank 0 if in SPL
OMAP3 relied on the memory config done by X-loader or Configuration Header. This
has to be reworked for the implementation of a SPL. This patch configures RAM
bank 0 if CONFIG_SPL_BUILD is set. Settings for Micron-RAM used by devkit8000
are added to mem.h
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 2a7970b..0dd1955 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -8,6 +8,9 @@
* Copyright (C) 2004-2010
* Texas Instruments Incorporated - http://www.ti.com/
*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
* Author :
* Vaibhav Hiremath <hvaibhav@ti.com>
*
@@ -132,6 +135,33 @@
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
}
+
+/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
+ * to prevent this to be build in non-SPL build */
+#ifdef CONFIG_SPL_BUILD
+ /* If we use a SPL there is no x-loader nor config header so we have
+ * to do the job ourselfs
+ */
+ if (cs == CS0) {
+ sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+ /* General SDRC config */
+ writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
+ writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
+
+ /* AC timings */
+ writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
+ writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
+
+ /* Initialize */
+ writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+ writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+ writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+ writel(V_MR, &sdrc_base->cs[cs].mr);
+ }
+#endif
/*
* SDRC timings are set up by x-load or config header
@@ -139,7 +169,7 @@
* Older x-loads configure only CS0
* configure CS1 to handle this ommission
*/
- if (cs) {
+ if (cs == CS1) {
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
writel(readl(&sdrc_base->cs[CS0].mcfg),
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index f165949..8e28f77 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -128,6 +128,33 @@
(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
(MICRON_TWTR_165 << 16))
+#define MICRON_RAMTYPE 0x1
+#define MICRON_DDRTYPE 0x0
+#define MICRON_DEEPPD 0x1
+#define MICRON_B32NOT16 0x1
+#define MICRON_BANKALLOCATION 0x2
+#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2)
+#define MICRON_ADDRMUXLEGACY 0x1
+#define MICRON_CASWIDTH 0x5
+#define MICRON_RASWIDTH 0x2
+#define MICRON_LOCKSTATUS 0x0
+#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
+ (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
+ (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
+ (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
+ (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
+
+#define MICRON_ARCV 2030
+#define MICRON_ARE 0x1
+#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
+
+#define MICRON_BL 0x2
+#define MICRON_SIL 0x0
+#define MICRON_CASL 0x3
+#define MICRON_WBST 0x0
+#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
+ (MICRON_SIL << 3) | (MICRON_BL))
+
/*
* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
* ACTIMA
@@ -171,10 +198,15 @@
#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
#endif
+
#ifdef CONFIG_OMAP3_MICRON_DDR
#define V_ACTIMA_165 MICRON_V_ACTIMA_165
#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#define V_MCFG MICRON_V_MCFG
+#define V_RFR_CTRL MICRON_V_RFR_CTRL
+#define V_MR MICRON_V_MR
#endif
+
#ifdef CONFIG_OMAP3_NUMONYX_DDR
#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
@@ -184,6 +216,10 @@
#error "Please choose the right DDR type in config header"
#endif
+#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
+#error "Please choose the right DDR type in config header"
+#endif
+
/*
* GPMC settings -
* Definitions is as per the following format