commit ed49a6afeabb2078050936828b765b70f47c7a6e
author Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Sat Jun 07 20:51:56 2008 +0900
committer Shinya Kuribayashi <shinya.kuribayashi@necel.com> Sat Jun 07 20:51:56 2008 +0900
tree 2078062f2ecb762e6b15b5b3e628a946ca409520
parent 6c6b2614970ff395943c4a1ef4d22ff7d5765415

[MIPS] Rename Alchemy processor configs into CONFIG_SOC_*

CONFIG_SOC_AU1X00

  Common Alchemy Au1x00 stuff. All Alchemy processor based machines
  need to have this config as a system type specifier.

CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550

  Machine type specifiers. Each port should have one of aboves.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

include/asm-mips/addrspace.h

diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 767804c..3a1e6d6 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -131,13 +131,13 @@
  * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
 /* We use a 36 bit physical address map here and
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else	/* !CONFIG_AU1X00 */
+#else	/* !CONFIG_SOC_AU1X00 */
 #define UNCACHED_SDRAM(a) KSEG1ADDR(a)
-#endif	/* CONFIG_AU1X00 */
+#endif	/* CONFIG_SOC_AU1X00 */
 #endif	/* __ASSEMBLY__ */
 
 /*

include/asm-mips/au1x00.h

diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 6a33197..2a948e8 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -137,7 +137,7 @@
 #define CP0_DEBUG		$23
 
 /* SDRAM Controller */
-#ifdef CONFIG_AU1550
+#ifdef CONFIG_SOC_AU1550
 
 #define MEM_SDMODE0                0xB4000800
 #define MEM_SDMODE1                0xB4000808
@@ -156,7 +156,7 @@
 #define MEM_SDWRMD1                0xB4000888
 #define MEM_SDWRMD2                0xB4000890
 
-#else /* CONFIG_AU1550 */
+#else /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004
@@ -174,7 +174,7 @@
 #define MEM_SDWRMD1                0xB4000028
 #define MEM_SDWRMD2                0xB400002C
 
-#endif /* CONFIG_AU1550 */
+#endif /* CONFIG_SOC_AU1550 */
 
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034