arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fec4c7a..0064fc8 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -127,7 +127,8 @@
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
- cm_basic_init(cm_default_cfg);
+ if (cm_basic_init(cm_default_cfg))
+ hang();
/* Enable bootrom to configure IOs. */
sysmgr_config_warmrstcfgio(1);