x86: gpio: Correct GPIO setup ordering
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.
Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 403851b..40f4958 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -12,6 +12,7 @@
struct ich6_bank_platdata {
uint16_t base_addr;
const char *bank_name;
+ int offset;
};
#define GPIO_MODE_NATIVE 0
@@ -146,6 +147,10 @@
} set3;
};
+/*
+ * Deprecated functions to set up the GPIO map. The device tree should be used
+ * instead.
+ */
int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index 527ed6d..c81d033 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -279,6 +279,7 @@
debug("%s: Invalid register offset %d\n", __func__, offset);
return -EINVAL;
}
+ plat->offset = offset;
plat->base_addr = gpiobase + offset;
plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
"bank-name", NULL);
@@ -293,7 +294,8 @@
struct ich6_bank_priv *bank = dev_get_priv(dev);
if (gd->arch.gpio_map) {
- setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
+ setup_pch_gpios(plat->base_addr - plat->offset,
+ gd->arch.gpio_map);
gd->arch.gpio_map = NULL;
}