spi: Support half-duplex mode in FDT decode
This parameter should also be supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
diff --git a/doc/device-tree-bindings/spi/spi-bus.txt b/doc/device-tree-bindings/spi/spi-bus.txt
index 800dafe..5c8720a 100644
--- a/doc/device-tree-bindings/spi/spi-bus.txt
+++ b/doc/device-tree-bindings/spi/spi-bus.txt
@@ -59,6 +59,8 @@
used for MOSI. Defaults to 1 if not present.
- spi-rx-bus-width - (optional) The bus width(number of data wires) that
used for MISO. Defaults to 1 if not present.
+- spi-half-duplex - (optional) Indicates that the SPI bus should wait for
+ a header byte before reading data from the slave.
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).