commit ebbac2f28a5d51da0b54dd70210d656f6aa1931d
author Michal Simek <michal.simek@xilinx.com> Thu Sep 01 12:51:27 2016 +0200
committer Michal Simek <michal.simek@xilinx.com> Thu Sep 22 07:33:20 2016 +0200
tree 76d280022ddbb3deeac9341bea8c7d5306904017
parent 76d0a77f11b6405510af43dbb47a8684040b1bbd

spi: zynq: Use variable to remove u32 to u64 conversions

Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
drivers/spi/zynq_spi.c: In function ‘zynq_spi_release_bus’:
drivers/spi/zynq_spi.c:177:9: warning: large integer implicitly
truncated to unsigned type [-Woverflow]
  writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
         ^
./arch/arm/include/asm/io.h:146:34: note: in definition of macro
‘writel’
 #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v;
})
                                  ^
This patch is using one variable to do conversion via u32 variable.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>

drivers/spi/zynq_spi.c

diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 09ae1be..7a176a2 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -92,7 +92,8 @@
 	u32 confr;
 
 	/* Disable SPI */
-	writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
+	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+	writel(~confr, &regs->enr);
 
 	/* Disable Interrupts */
 	writel(ZYNQ_SPI_IXR_ALL_MASK, &regs->idr);
@@ -173,8 +174,10 @@
 	struct udevice *bus = dev->parent;
 	struct zynq_spi_priv *priv = dev_get_priv(bus);
 	struct zynq_spi_regs *regs = priv->regs;
+	u32 confr;
 
-	writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, &regs->enr);
+	confr = ZYNQ_SPI_ENR_SPI_EN_MASK;
+	writel(~confr, &regs->enr);
 
 	return 0;
 }