| commit | c6bfa35c86419d39a13eb3c214037d0571d2aba2 | [log] [tgz] |
|---|---|---|
| author | Leo Yu-Chi Liang <ycliang@andestech.com> | Tue May 28 20:49:57 2024 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Thu May 30 16:01:09 2024 +0800 |
| tree | d31d21ebf1adffbefec27966a1ea8a417515713e | |
| parent | f98a80a8f127576e71193d64f0e89275f5a5e7cb [diff] |
riscv: remove cache enablement in start.S Cache could be enabled in harts_early_init board-specific hook, so remove cache enablement in start.S Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>