| commit | eb10f6a2b76dfd308163ecc515e6296c07126a73 | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Wed Feb 23 16:17:38 2022 +0100 |
| committer | Michal Simek <michal.simek@xilinx.com> | Mon Mar 07 16:33:47 2022 +0100 |
| tree | 69e0c48348aeefe300530cc4603d5fbe08d18396 | |
| parent | 1a9fe83841e2cacdcb46c70c2e712c5bcf006b03 [diff] [blame] |
arm64: zynqmp: Setup clock for DP and DPDMA Clocks are coming from shared HW design where these frequencies should be aligned with PLL setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/04454c50d0d13e450976942085d763ab5aa38f98.1645629459.git.michal.simek@xilinx.com
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 01b14eb..35247b0 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -95,10 +95,12 @@ status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 {