diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index d778db6..9545e0a 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -55,6 +55,7 @@
 			       struct cpg_mssr_info *info, struct clk *parent)
 {
 	const struct cpg_core_clk *core;
+	u8 shift;
 	int ret;
 
 	if (!renesas_clk_is_mod(clk)) {
@@ -63,8 +64,9 @@
 			return ret;
 
 		if (core->type == CLK_TYPE_GEN3_MDSEL) {
+			shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
 			parent->dev = clk->dev;
-			parent->id = core->parent >> (priv->sscg ? 16 : 0);
+			parent->id = core->parent >> shift;
 			parent->id &= 0xffff;
 			return 0;
 		}
@@ -183,6 +185,7 @@
 					priv->cpg_pll_config;
 	u32 value, div;
 	u64 rate = 0;
+	u8 shift;
 	int ret;
 
 	debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
@@ -277,11 +280,11 @@
 						"FIXED");
 
 	case CLK_TYPE_GEN3_MDSEL:
-		div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
+		shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
+		div = (core->div >> shift) & 0xffff;
 		rate = gen3_clk_get_rate64(&parent) / div;
 		debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
-		      __func__, __LINE__,
-		      (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
+		      __func__, __LINE__, (core->parent >> shift) & 0xffff,
 		      div, rate);
 		return rate;
 
@@ -407,7 +410,6 @@
 	struct cpg_mssr_info *info =
 		(struct cpg_mssr_info *)dev_get_driver_data(dev);
 	fdt_addr_t rst_base;
-	u32 cpg_mode;
 	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
@@ -423,15 +425,13 @@
 	if (rst_base == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	cpg_mode = readl(rst_base + info->reset_modemr_offset);
+	priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
 
 	priv->cpg_pll_config =
-		(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
+		(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(priv->cpg_mode);
 	if (!priv->cpg_pll_config->extal_div)
 		return -EINVAL;
 
-	priv->sscg = !(cpg_mode & BIT(12));
-
 	if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
 		priv->info->status_regs = mstpsr;
 		priv->info->control_regs = smstpcr;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 200e4ad..894e376 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -132,7 +132,7 @@
 	struct cpg_mssr_info	*info;
 	struct clk		clk_extal;
 	struct clk		clk_extalr;
-	bool			sscg;
+	u32			cpg_mode;
 	const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
 };