Decreases code size of the nand_spl
The canyonland boards nand_spl size is just under the maximum 4KByte size. This
patch decreases the size of the nand_spl to make a previous commit - commit
65a9db7be0868be91ba81b9b5bf821de82e6d9b0 - fit in the nand_spl.
Signed-off-by: Alex Waterman <awaterman@dawning.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index 4a96878..4628524 100644
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -77,6 +77,8 @@
{
struct nand_chip *this = mtd->priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ void (*hwctrl)(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl) = this->cmd_ctrl;
if (this->dev_ready)
while (!this->dev_ready(mtd))
@@ -95,25 +97,25 @@
offs >>= 1;
/* Begin command latch cycle */
- this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- this->cmd_ctrl(mtd, offs & 0xff,
+ hwctrl(mtd, offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff),
+ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
/* One more address cycle for devices > 128MiB */
- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
/* Latch in address */
- this->cmd_ctrl(mtd, NAND_CMD_READSTART,
+ hwctrl(mtd, NAND_CMD_READSTART,
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready