tree e11d8aab8ed9bf861b7cd9040717fbeb96c11a22
parent 08687cc49b459a09aab0778ad1325b652c45767c
author Anthony Felice <tony.felice@timesys.com> 1444423119 -0400
committer Stefano Babic <sbabic@denx.de> 1444980806 +0200

vf610twr: Fix typo in DRAM init

This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>