commit e91957737e42c5407e81c7870d55a64bf30b4739
author Marc Zyngier <marc.zyngier@arm.com> Sat Jul 12 14:23:59 2014 +0100
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Mon Jul 28 17:06:19 2014 +0200
tree a4865793a45efcb3552f5e9e5cc256ad7f4fab27
parent 915a09efd86c030114d75ab35aa086235e1ec6ba

ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

arch/arm/cpu/armv7/nonsec_virt.S

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09..12de5c2 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -46,6 +46,7 @@
 #endif
 
 	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
+	isb
 
 #ifdef CONFIG_ARMV7_VIRT
 	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value