tree 04f4419564cb23a30063421916038f6accde3dd7
parent ece3cc0915190319703f3131c738c1b3471c4db9
author Dinh Nguyen <dinguyen@opensource.altera.com> 1444922016 -0500
committer Marek Vasut <marex@denx.de> 1445039251 +0200

arm: socfpga: enable data/inst prefetch and shared override in the L2

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>