diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 5adfd9b..8a9f2a6 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -8,7 +8,7 @@
 			filename = "spl/sunxi-spl.bin";
 		};
 		u-boot-img {
-			pos = <CONFIG_SPL_PAD_TO>;
+			offset = <CONFIG_SPL_PAD_TO>;
 		};
 	};
 };
diff --git a/arch/arm/dts/tegra-u-boot.dtsi b/arch/arm/dts/tegra-u-boot.dtsi
index 4f692ee..fe19619 100644
--- a/arch/arm/dts/tegra-u-boot.dtsi
+++ b/arch/arm/dts/tegra-u-boot.dtsi
@@ -15,7 +15,7 @@
 			u-boot-spl {
 			};
 			u-boot {
-				pos = <(U_BOOT_OFFSET)>;
+				offset = <(U_BOOT_OFFSET)>;
 			};
 		};
 
@@ -26,7 +26,7 @@
 			u-boot-spl {
 			};
 			u-boot {
-				pos = <(U_BOOT_OFFSET)>;
+				offset = <(U_BOOT_OFFSET)>;
 			};
 		};
 
@@ -36,7 +36,7 @@
 			u-boot-spl {
 			};
 			u-boot-nodtb {
-				pos = <(U_BOOT_OFFSET)>;
+				offset = <(U_BOOT_OFFSET)>;
 			};
 		};
 	};
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1253fa5..1050236 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -11,7 +11,7 @@
 	binman {
 		filename = "u-boot.rom";
 		end-at-4gb;
-		sort-by-pos;
+		sort-by-offset;
 		pad-byte = <0xff>;
 		size = <CONFIG_ROM_SIZE>;
 #ifdef CONFIG_HAVE_INTEL_ME
@@ -24,18 +24,18 @@
 #endif
 #ifdef CONFIG_SPL
 		u-boot-spl-with-ucode-ptr {
-			pos = <CONFIG_SPL_TEXT_BASE>;
+			offset = <CONFIG_SPL_TEXT_BASE>;
 		};
 
 		u-boot-dtb-with-ucode2 {
 			type = "u-boot-dtb-with-ucode";
 		};
 		u-boot {
-			pos = <0xfff00000>;
+			offset = <0xfff00000>;
 		};
 #else
 		u-boot-with-ucode-ptr {
-			pos = <CONFIG_SYS_TEXT_BASE>;
+			offset = <CONFIG_SYS_TEXT_BASE>;
 		};
 #endif
 		u-boot-dtb-with-ucode {
@@ -45,45 +45,45 @@
 		};
 #ifdef CONFIG_HAVE_MRC
 		intel-mrc {
-			pos = <CONFIG_X86_MRC_ADDR>;
+			offset = <CONFIG_X86_MRC_ADDR>;
 		};
 #endif
 #ifdef CONFIG_HAVE_FSP
 		intel-fsp {
 			filename = CONFIG_FSP_FILE;
-			pos = <CONFIG_FSP_ADDR>;
+			offset = <CONFIG_FSP_ADDR>;
 		};
 #endif
 #ifdef CONFIG_HAVE_CMC
 		intel-cmc {
 			filename = CONFIG_CMC_FILE;
-			pos = <CONFIG_CMC_ADDR>;
+			offset = <CONFIG_CMC_ADDR>;
 		};
 #endif
 #ifdef CONFIG_HAVE_VGA_BIOS
 		intel-vga {
 			filename = CONFIG_VGA_BIOS_FILE;
-			pos = <CONFIG_VGA_BIOS_ADDR>;
+			offset = <CONFIG_VGA_BIOS_ADDR>;
 		};
 #endif
 #ifdef CONFIG_HAVE_VBT
 		intel-vbt {
 			filename = CONFIG_VBT_FILE;
-			pos = <CONFIG_VBT_ADDR>;
+			offset = <CONFIG_VBT_ADDR>;
 		};
 #endif
 #ifdef CONFIG_HAVE_REFCODE
 		intel-refcode {
-			pos = <CONFIG_X86_REFCODE_ADDR>;
+			offset = <CONFIG_X86_REFCODE_ADDR>;
 		};
 #endif
 #ifdef CONFIG_SPL
 		x86-start16-spl {
-			pos = <CONFIG_SYS_X86_START16>;
+			offset = <CONFIG_SYS_X86_START16>;
 		};
 #else
 		x86-start16 {
-			pos = <CONFIG_SYS_X86_START16>;
+			offset = <CONFIG_SYS_X86_START16>;
 		};
 #endif
 	};