| commit | 1790bce600368f0462c3cde530e9a9e9827f8374 | [log] [tgz] |
|---|---|---|
| author | Pragnesh Patel <pragnesh.patel@sifive.com> | Fri May 29 11:33:30 2020 +0530 |
| committer | Andes <uboot@andestech.com> | Thu Jun 04 09:44:08 2020 +0800 |
| tree | 6e3f2b6ac2468caf0a958bca00e9136cff2befc6 | |
| parent | 54ce0e05409a4884ce193592245b3ae93b0201d6 [diff] |
clk: sifive: fu540-prci: Add ddr clock initialization Release ddr clock reset once clock is initialized Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>