tree 1d88fa393639b8161eeddb1c3968798a436e3099
parent 0cc228e97f6b6197b1d3e87335f3b3c97e2e0a81
author Chen-Yu Tsai <wens@csie.org> 1504187868 +0800
committer Jagan Teki <jagan@amarulasolutions.com> 1504275587 +0530

mmc: sunxi: Only update timing mode bit when enabling new timing mode

When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>