commit e751dfd21102059e081c8c7b94ca1466d63bf376
author Bo Shen <voice.shen@atmel.com> Mon Dec 15 13:24:36 2014 +0800
committer Andreas Bießmann <andreas.devel@googlemail.com> Sat Feb 07 23:42:51 2015 +0100
tree f8222bd2d79101fdd3db4216df4b077185649241
parent e1ec15c0222ff582d87427a071d1c87dc4eb8dc3

ARM: atmel: sama5d4: can access DDR in interleave mode

The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>

arch/arm/cpu/at91-common/mpddrc.c

diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
index 44798e6..beec13d 100644
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -19,7 +19,7 @@
 
 static int ddr2_decodtype_is_seq(u32 cr)
 {
-#if defined(CONFIG_SAMA5D3)
+#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
 	if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
 		return 0;
 #endif