net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 1559bf6..1818b45 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -89,7 +89,13 @@
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
-#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL BIT(20)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN BIT(19)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII (1 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
#define FEC_QUIRK_ENET_MAC
#ifdef CONFIG_ARMV8_PSCI /* Final jump location */
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 494bfbe..1546c9b 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -15,6 +15,7 @@
#include <errno.h>
#include <linux/bitops.h>
#include <linux/delay.h>
+#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -825,7 +826,7 @@
return 0;
}
-#ifdef CONFIG_DWC_ETH_QOS
+#if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
int set_clk_eqos(enum enet_freq type)
{
u32 target;
@@ -872,6 +873,52 @@
return 0;
}
+
+static int imx8mp_eqos_interface_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ clrbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ setbits_le32(&gpr->gpr[1],
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#else
+static int imx8mp_eqos_interface_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ return 0;
+}
#endif
#ifdef CONFIG_FEC_MXC
@@ -922,3 +969,13 @@
return 0;
}
#endif
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t interface_type)
+{
+ if (IS_ENABLED(CONFIG_IMX8MP) &&
+ IS_ENABLED(CONFIG_DWC_ETH_QOS) &&
+ device_is_compatible(dev, "nxp,imx8mp-dwmac-eqos"))
+ return imx8mp_eqos_interface_init(dev, interface_type);
+
+ return -EINVAL;
+}