* Some code cleanup
* Patch by Josef Baumgartner, 10 Feb 2004:
Fixes for Coldfire port
* Patch by Brad Kemp, 11 Feb 2004:
Fix CFI flash driver problems
diff --git a/board/evb64260/ecctest.c b/board/evb64260/ecctest.c
index e7c58b3..5d3679a 100644
--- a/board/evb64260/ecctest.c
+++ b/board/evb64260/ecctest.c
@@ -1,91 +1,111 @@
+indent: Standard input:27: Warning:old style assignment ambiguity in "=*". Assuming "= *"
+
#ifdef ECC_TEST
-static inline void ecc_off(void)
+static inline void ecc_off (void)
{
- *(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) &= ~0x00200000;
+ *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) &= ~0x00200000;
}
-static inline void ecc_on(void)
+static inline void ecc_on (void)
{
- *(volatile int *)(INTERNAL_REG_BASE_ADDR+0x4b4) |= 0x00200000;
+ *(volatile int *) (INTERNAL_REG_BASE_ADDR + 0x4b4) |= 0x00200000;
}
-static int putshex(const char *buf, int len)
+static int putshex (const char *buf, int len)
{
- int i;
- for (i=0;i<len;i++) {
- printf("%02x", buf[i]);
- }
- return 0;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ printf ("%02x", buf[i]);
+ }
+ return 0;
}
-static int char_memcpy(void *d, const void *s, int len)
+static int char_memcpy (void *d, const void *s, int len)
{
- int i;
- char *cd=d;
- const char *cs=s;
- for(i=0;i<len;i++) {
- *(cd++)=*(cs++);
- }
- return 0;
+ int i;
+ char *cd = d;
+ const char *cs = s;
+
+ for (i = 0; i < len; i++) {
+ *(cd++) = *(cs++);
+ }
+ return 0;
}
-static int memory_test(char *buf)
+static int memory_test (char *buf)
{
- const char src[][16]={
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
- {0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01},
- {0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02},
- {0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04,0x04},
- {0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08},
- {0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},
- {0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20},
- {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
- {0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80},
- {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55},
- {0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa},
- {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}
- };
- const int foo[] = {0};
- int i,j,a;
+ const char src[][16] = {
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01},
+ {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02, 0x02, 0x02},
+ {0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0x04, 0x04, 0x04},
+ {0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+ 0x08, 0x08, 0x08, 0x08, 0x08, 0x08},
+ {0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10,
+ 0x10, 0x10, 0x10, 0x10, 0x10, 0x10},
+ {0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20},
+ {0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40},
+ {0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+ 0x80, 0x80, 0x80, 0x80, 0x80, 0x80},
+ {0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+ 0x55, 0x55, 0x55, 0x55, 0x55, 0x55},
+ {0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+ 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa},
+ {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}
+ };
+ const int foo[] = { 0 };
+ int i, j, a;
- printf("\ntest @ %d %p\n", foo[0], buf);
- for(i=0;i<12;i++) {
- for(a=0;a<8;a++) {
- const char *s=src[i]+a;
- int align=(unsigned)(s)&0x7;
- /* ecc_off(); */
- memcpy(buf,s,8);
- /* ecc_on(); */
- putshex(s,8);
- if(memcmp(buf,s,8)) {
- putc('\n');
- putshex(buf,8);
- printf(" [FAIL] (%p) align=%d\n", s, align);
- for(j=0;j<8;j++) {
- s[j]==buf[j]?puts(" "):printf("%02x", (s[j])^(buf[j]));
- }
- putc('\n');
- } else {
- printf(" [PASS] (%p) align=%d\n", s, align);
- }
- /* ecc_off(); */
- char_memcpy(buf,s,8);
- /* ecc_on(); */
- putshex(s,8);
- if(memcmp(buf,s,8)) {
- putc('\n');
- putshex(buf,8);
- printf(" [FAIL] (%p) align=%d\n", s, align);
- for(j=0;j<8;j++) {
- s[j]==buf[j]?puts(" "):printf("%02x", (s[j])^(buf[j]));
+ printf ("\ntest @ %d %p\n", foo[0], buf);
+ for (i = 0; i < 12; i++) {
+ for (a = 0; a < 8; a++) {
+ const char *s = src[i] + a;
+ int align = (unsigned) (s) & 0x7;
+
+ /* ecc_off(); */
+ memcpy (buf, s, 8);
+ /* ecc_on(); */
+ putshex (s, 8);
+ if (memcmp (buf, s, 8)) {
+ putc ('\n');
+ putshex (buf, 8);
+ printf (" [FAIL] (%p) align=%d\n", s, align);
+ for (j = 0; j < 8; j++) {
+ s[j] == buf[j] ? puts (" ") :
+ printf ("%02x",
+ (s[j]) ^ (buf[j]));
+ }
+ putc ('\n');
+ } else {
+ printf (" [PASS] (%p) align=%d\n", s, align);
+ }
+ /* ecc_off(); */
+ char_memcpy (buf, s, 8);
+ /* ecc_on(); */
+ putshex (s, 8);
+ if (memcmp (buf, s, 8)) {
+ putc ('\n');
+ putshex (buf, 8);
+ printf (" [FAIL] (%p) align=%d\n", s, align);
+ for (j = 0; j < 8; j++) {
+ s[j] == buf[j] ? puts (" ") :
+ printf ("%02x",
+ (s[j]) ^ (buf[j]));
+ }
+ putc ('\n');
+ } else {
+ printf (" [PASS] (%p) align=%d\n", s, align);
+ }
}
- putc('\n');
- } else {
- printf(" [PASS] (%p) align=%d\n", s, align);
- }
}
- }
- return 0;
+ return 0;
}
#endif
diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c
index ef463c3..0abc7d4 100644
--- a/board/evb64260/eth_addrtbl.c
+++ b/board/evb64260/eth_addrtbl.c
@@ -13,66 +13,68 @@
#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
-static u32 addressTableHashMode[ GAL_ETH_DEVS ] = { 0, };
-static u32 addressTableHashSize[ GAL_ETH_DEVS ] = { 0, };
-static addrTblEntry *addressTableBase[ GAL_ETH_DEVS ] = { 0, };
-static void *realAddrTableBase[ GAL_ETH_DEVS ] = { 0, };
+static u32 addressTableHashMode[GAL_ETH_DEVS] = { 0, };
+static u32 addressTableHashSize[GAL_ETH_DEVS] = { 0, };
+static addrTblEntry *addressTableBase[GAL_ETH_DEVS] = { 0, };
+static void *realAddrTableBase[GAL_ETH_DEVS] = { 0, };
-static const u32 hashLength[ 2 ] = {
- (0x8000), /* 8K * 4 entries */
- (0x8000/16), /* 512 * 4 entries */
+static const u32 hashLength[2] = {
+ (0x8000), /* 8K * 4 entries */
+ (0x8000 / 16), /* 512 * 4 entries */
};
/* Initialize the address table for a port, if needed */
-unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
+unsigned int initAddressTable (u32 port, u32 hashMode, u32 hashSizeSelector)
{
- unsigned int tableBase;
+ unsigned int tableBase;
- if( port < 0 || port >= GAL_ETH_DEVS ) {
- printf("%s: Invalid port number %d\n", __FUNCTION__, port );
+ if (port < 0 || port >= GAL_ETH_DEVS) {
+ printf ("%s: Invalid port number %d\n", __FUNCTION__, port);
return 0;
}
if (hashMode > 1) {
- printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port );
+ printf ("%s: Invalid Hash Mode %d\n", __FUNCTION__, port);
return 0;
}
- if ( realAddrTableBase[port] &&
- ( addressTableHashSize[port] != hashSizeSelector )) {
+ if (realAddrTableBase[port] &&
+ (addressTableHashSize[port] != hashSizeSelector)) {
/* we have been here before,
* but now we want a different sized table
*/
- free( realAddrTableBase[port] );
+ free (realAddrTableBase[port]);
realAddrTableBase[port] = 0;
addressTableBase[port] = 0;
}
- tableBase = (unsigned int)addressTableBase[port];
+ tableBase = (unsigned int) addressTableBase[port];
/* we get called for every probe, so only do this once */
- if ( !tableBase ) {
- int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry);
+ if (!tableBase) {
+ int bytes =
+ hashLength[hashSizeSelector] * sizeof (addrTblEntry);
- tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64);
+ tableBase = (unsigned int) realAddrTableBase[port] =
+ malloc (bytes + 64);
- if(!tableBase)
- {
- printf("%s: alloc memory failed \n", __FUNCTION__);
+ if (!tableBase) {
+ printf ("%s: alloc memory failed \n", __FUNCTION__);
return 0;
}
- /* align to octal byte */
- if(tableBase&63) tableBase=(tableBase+63) & ~63;
+ /* align to octal byte */
+ if (tableBase & 63)
+ tableBase = (tableBase + 63) & ~63;
- addressTableHashMode[port] = hashMode;
- addressTableHashSize[port] = hashSizeSelector;
- addressTableBase[port] = (addrTblEntry *)tableBase;
+ addressTableHashMode[port] = hashMode;
+ addressTableHashSize[port] = hashSizeSelector;
+ addressTableBase[port] = (addrTblEntry *) tableBase;
- memset((void *)tableBase,0,bytes);
+ memset ((void *) tableBase, 0, bytes);
}
- return tableBase;
+ return tableBase;
}
/*
@@ -87,61 +89,61 @@
* Outputs
* return the calculated entry.
*/
-u32
-hashTableFunction( u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
+u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode)
{
- u32 hashResult;
- u32 addrH;
- u32 addrL;
- u32 addr0;
- u32 addr1;
- u32 addr2;
- u32 addr3;
- u32 addrHSwapped;
- u32 addrLSwapped;
+ u32 hashResult;
+ u32 addrH;
+ u32 addrL;
+ u32 addr0;
+ u32 addr1;
+ u32 addr2;
+ u32 addr3;
+ u32 addrHSwapped;
+ u32 addrLSwapped;
- addrH = NIBBLE_SWAPPING_16_BIT( macH );
- addrL = NIBBLE_SWAPPING_32_BIT( macL );
+ addrH = NIBBLE_SWAPPING_16_BIT (macH);
+ addrL = NIBBLE_SWAPPING_32_BIT (macL);
- addrHSwapped = FLIP_4_BITS( addrH & 0xf )
- + ((FLIP_4_BITS( (addrH >> 4) & 0xf)) << 4)
- + ((FLIP_4_BITS( (addrH >> 8) & 0xf)) << 8)
- + ((FLIP_4_BITS( (addrH >> 12) & 0xf)) << 12);
+ addrHSwapped = FLIP_4_BITS (addrH & 0xf)
+ + ((FLIP_4_BITS ((addrH >> 4) & 0xf)) << 4)
+ + ((FLIP_4_BITS ((addrH >> 8) & 0xf)) << 8)
+ + ((FLIP_4_BITS ((addrH >> 12) & 0xf)) << 12);
- addrLSwapped = FLIP_4_BITS( addrL & 0xf )
- + ((FLIP_4_BITS( (addrL >> 4) & 0xf)) << 4)
- + ((FLIP_4_BITS( (addrL >> 8) & 0xf)) << 8)
- + ((FLIP_4_BITS( (addrL >> 12) & 0xf)) << 12)
- + ((FLIP_4_BITS( (addrL >> 16) & 0xf)) << 16)
- + ((FLIP_4_BITS( (addrL >> 20) & 0xf)) << 20)
- + ((FLIP_4_BITS( (addrL >> 24) & 0xf)) << 24)
- + ((FLIP_4_BITS( (addrL >> 28) & 0xf)) << 28);
+ addrLSwapped = FLIP_4_BITS (addrL & 0xf)
+ + ((FLIP_4_BITS ((addrL >> 4) & 0xf)) << 4)
+ + ((FLIP_4_BITS ((addrL >> 8) & 0xf)) << 8)
+ + ((FLIP_4_BITS ((addrL >> 12) & 0xf)) << 12)
+ + ((FLIP_4_BITS ((addrL >> 16) & 0xf)) << 16)
+ + ((FLIP_4_BITS ((addrL >> 20) & 0xf)) << 20)
+ + ((FLIP_4_BITS ((addrL >> 24) & 0xf)) << 24)
+ + ((FLIP_4_BITS ((addrL >> 28) & 0xf)) << 28);
- addrH = addrHSwapped;
- addrL = addrLSwapped;
+ addrH = addrHSwapped;
+ addrL = addrLSwapped;
- if( hash_mode == 0 ) {
- addr0 = (addrL >> 2) & 0x03f;
- addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
- addr2 = (addrL >> 15) & 0x1ff;
- addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
- } else {
- addr0 = FLIP_6_BITS( addrL & 0x03f );
- addr1 = FLIP_9_BITS( ((addrL >> 6) & 0x1ff));
- addr2 = FLIP_9_BITS( (addrL >> 15) & 0x1ff);
- addr3 = FLIP_9_BITS( (((addrL >> 24) & 0x0ff) | ((addrH & 0x1) << 8)));
- }
+ if (hash_mode == 0) {
+ addr0 = (addrL >> 2) & 0x03f;
+ addr1 = (addrL & 0x003) | ((addrL >> 8) & 0x7f) << 2;
+ addr2 = (addrL >> 15) & 0x1ff;
+ addr3 = ((addrL >> 24) & 0x0ff) | ((addrH & 1) << 8);
+ } else {
+ addr0 = FLIP_6_BITS (addrL & 0x03f);
+ addr1 = FLIP_9_BITS (((addrL >> 6) & 0x1ff));
+ addr2 = FLIP_9_BITS ((addrL >> 15) & 0x1ff);
+ addr3 = FLIP_9_BITS ((((addrL >> 24) & 0x0ff) |
+ ((addrH & 0x1) << 8)));
+ }
- hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+ hashResult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
- if( HashSize == _8K_TABLE ) {
- hashResult = hashResult & 0xffff;
- } else {
- hashResult = hashResult & 0x07ff;
- }
+ if (HashSize == _8K_TABLE) {
+ hashResult = hashResult & 0xffff;
+ } else {
+ hashResult = hashResult & 0x07ff;
+ }
- return( hashResult );
+ return (hashResult);
}
@@ -160,66 +162,59 @@
* TRUE if success.
* FALSE if table full
*/
-int
-addAddressTableEntry(
- u32 port,
- u32 macH,
- u32 macL,
- u32 rd,
- u32 skip )
+int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip)
{
- addrTblEntry *entry;
- u32 newHi;
- u32 newLo;
- u32 i;
+ addrTblEntry *entry;
+ u32 newHi;
+ u32 newLo;
+ u32 i;
- newLo = (((macH >> 4) & 0xf) << 15)
- | (((macH >> 0) & 0xf) << 11)
- | (((macH >> 12) & 0xf) << 7)
- | (((macH >> 8) & 0xf) << 3)
- | (((macL >> 20) & 0x1) << 31)
- | (((macL >> 16) & 0xf) << 27)
- | (((macL >> 28) & 0xf) << 23)
- | (((macL >> 24) & 0xf) << 19)
- | (skip << SKIP_BIT) | (rd << 2) | VALID;
+ newLo = (((macH >> 4) & 0xf) << 15)
+ | (((macH >> 0) & 0xf) << 11)
+ | (((macH >> 12) & 0xf) << 7)
+ | (((macH >> 8) & 0xf) << 3)
+ | (((macL >> 20) & 0x1) << 31)
+ | (((macL >> 16) & 0xf) << 27)
+ | (((macL >> 28) & 0xf) << 23)
+ | (((macL >> 24) & 0xf) << 19)
+ | (skip << SKIP_BIT) | (rd << 2) | VALID;
- newHi = (((macL >> 4) & 0xf) << 15)
- | (((macL >> 0) & 0xf) << 11)
- | (((macL >> 12) & 0xf) << 7)
- | (((macL >> 8) & 0xf) << 3)
- | (((macL >> 21) & 0x7) << 0);
+ newHi = (((macL >> 4) & 0xf) << 15)
+ | (((macL >> 0) & 0xf) << 11)
+ | (((macL >> 12) & 0xf) << 7)
+ | (((macL >> 8) & 0xf) << 3)
+ | (((macL >> 21) & 0x7) << 0);
- /*
- * Pick the appropriate table, start scanning for free/reusable
- * entries at the index obtained by hashing the specified MAC address
- */
- entry = addressTableBase[port];
- entry += hashTableFunction( macH, macL, addressTableHashSize[port],
- addressTableHashMode[port] );
- for( i = 0; i < HOP_NUMBER; i++, entry++ ) {
- if( !(entry->lo & VALID) /*|| (entry->lo & SKIP)*/ ) {
- break;
- } else { /* if same address put in same position */
- if( ((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
- && (entry->hi == newHi) )
- {
- break;
- }
+ /*
+ * Pick the appropriate table, start scanning for free/reusable
+ * entries at the index obtained by hashing the specified MAC address
+ */
+ entry = addressTableBase[port];
+ entry += hashTableFunction (macH, macL, addressTableHashSize[port],
+ addressTableHashMode[port]);
+ for (i = 0; i < HOP_NUMBER; i++, entry++) {
+ if (!(entry->lo & VALID) /*|| (entry->lo & SKIP) */ ) {
+ break;
+ } else { /* if same address put in same position */
+ if (((entry->lo & 0xfffffff8) == (newLo & 0xfffffff8))
+ && (entry->hi == newHi)) {
+ break;
+ }
+ }
}
- }
- if( i == HOP_NUMBER ) {
- PRINTF( "addGT64260addressTableEntry: table section is full\n" );
- return( FALSE );
- }
+ if (i == HOP_NUMBER) {
+ PRINTF ("addGT64260addressTableEntry: table section is full\n");
+ return (FALSE);
+ }
- /*
- * Update the selected entry
- */
- entry->hi = newHi;
- entry->lo = newLo;
- DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE );
- return( TRUE );
+ /*
+ * Update the selected entry
+ */
+ entry->hi = newHi;
+ entry->lo = newLo;
+ DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE);
+ return (TRUE);
}
#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
index 22da746..e3172b2 100644
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -9,50 +9,62 @@
static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
#ifdef CONFIG_ZUMA_V2
- {0,0,0,0,0,0,0,29, [8 ... PCI_MAX_DEVICES-1]=0},
- {0,0,0,0,0,0,0,28, [8 ... PCI_MAX_DEVICES-1]=0}
-#else /* EVB??? This is a guess */
- {0,0,0,0,0,0,0,27,27, [9 ... PCI_MAX_DEVICES-1]=0},
- {0,0,0,0,0,0,0,29,29, [9 ... PCI_MAX_DEVICES-1]=0}
+ {0, 0, 0, 0, 0, 0, 0, 29,[8...PCI_MAX_DEVICES - 1] = 0},
+ {0, 0, 0, 0, 0, 0, 0, 28,[8...PCI_MAX_DEVICES - 1] = 0}
+#else /* EVB??? This is a guess */
+ {0, 0, 0, 0, 0, 0, 0, 27, 27,[9...PCI_MAX_DEVICES - 1] = 0},
+ {0, 0, 0, 0, 0, 0, 0, 29, 29,[9...PCI_MAX_DEVICES - 1] = 0}
#endif
};
-static const unsigned int pci_p2p_configuration_reg[]={
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION};
+static const unsigned int pci_p2p_configuration_reg[] = {
+ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
-static const unsigned int pci_configuration_address[]={
- PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS};
+static const unsigned int pci_configuration_address[] = {
+ PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
+};
-static const unsigned int pci_configuration_data[]={
- PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
- PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER};
+static const unsigned int pci_configuration_data[] = {
+ PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
+ PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
+};
-static const unsigned int pci_error_cause_reg[]={
- PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE};
+static const unsigned int pci_error_cause_reg[] = {
+ PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
+};
-static const unsigned int pci_arbiter_control[]={
- PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL};
+static const unsigned int pci_arbiter_control[] = {
+ PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
+};
-static const unsigned int pci_snoop_control_base_0_low[]={
- PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW};
-static const unsigned int pci_snoop_control_top_0[]={
- PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0};
+static const unsigned int pci_snoop_control_base_0_low[] = {
+ PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_snoop_control_top_0[] = {
+ PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
+};
-static const unsigned int pci_access_control_base_0_low[]={
- PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW};
-static const unsigned int pci_access_control_top_0[]={
- PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0};
+static const unsigned int pci_access_control_base_0_low[] = {
+ PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
+};
+static const unsigned int pci_access_control_top_0[] = {
+ PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
+};
static const unsigned int pci_scs_bank_size[2][4] = {
- {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
- PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
- {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
- PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}};
+ {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
+ PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
+ {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
+ PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
+};
static const unsigned int pci_p2p_configuration[] = {
- PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION};
+ PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
+};
-static unsigned int local_buses[] = { 0, 0};
+static unsigned int local_buses[] = { 0, 0 };
+
/********************************************************************
* pciWriteConfigReg - Write to a PCI configuration register
* - Make sure the GT is configured as a master before writing
@@ -71,28 +83,33 @@
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,unsigned int pciDevNum,unsigned int data)
+void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
+ unsigned int pciDevNum, unsigned int data)
{
- volatile unsigned int DataForAddrReg;
- unsigned int functionNum;
- unsigned int busNum = PCI_BUS(pciDevNum);
- unsigned int addr;
+ volatile unsigned int DataForAddrReg;
+ unsigned int functionNum;
+ unsigned int busNum = PCI_BUS (pciDevNum);
+ unsigned int addr;
- if(pciDevNum > 32) /* illegal device Number */
- return;
- if(pciDevNum == SELF) /* configure our configuration space. */
- {
- pciDevNum = (GTREGREAD(pci_p2p_configuration_reg[host]) >> 24) & 0x1f;
- busNum = GTREGREAD(pci_p2p_configuration_reg[host]) & 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg = ( regOffset | pciDevNum | functionNum | busNum) | BIT31;
- GT_REG_WRITE(pci_configuration_address[host],DataForAddrReg);
- GT_REG_READ(pci_configuration_address[host], &addr);
- if (addr != DataForAddrReg) return;
- GT_REG_WRITE(pci_configuration_data[host],data);
+ if (pciDevNum > 32) /* illegal device Number */
+ return;
+ if (pciDevNum == SELF) { /* configure our configuration space. */
+ pciDevNum =
+ (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+ 0x1f;
+ busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+ 0xff0000;
+ }
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xfc;
+ DataForAddrReg =
+ (regOffset | pciDevNum | functionNum | busNum) | BIT31;
+ GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+ GT_REG_READ (pci_configuration_address[host], &addr);
+ if (addr != DataForAddrReg)
+ return;
+ GT_REG_WRITE (pci_configuration_data[host], data);
}
/********************************************************************
@@ -113,30 +130,34 @@
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,unsigned int pciDevNum)
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+ unsigned int pciDevNum)
{
- volatile unsigned int DataForAddrReg;
+ volatile unsigned int DataForAddrReg;
unsigned int data;
- unsigned int functionNum;
- unsigned int busNum = PCI_BUS(pciDevNum);
+ unsigned int functionNum;
+ unsigned int busNum = PCI_BUS (pciDevNum);
- if(pciDevNum > 32) /* illegal device Number */
- return 0xffffffff;
- if(pciDevNum == SELF) /* configure our configuration space. */
- {
- pciDevNum = (GTREGREAD(pci_p2p_configuration_reg[host]) >> 24) & 0x1f;
- busNum = GTREGREAD(pci_p2p_configuration_reg[host]) & 0xff0000;
- }
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xfc;
- DataForAddrReg = (regOffset | pciDevNum | functionNum | busNum) | BIT31 ;
- GT_REG_WRITE(pci_configuration_address[host],DataForAddrReg);
- GT_REG_READ(pci_configuration_address[host], &data);
- if (data != DataForAddrReg)
- return 0xffffffff;
- GT_REG_READ(pci_configuration_data[host], &data);
- return data;
+ if (pciDevNum > 32) /* illegal device Number */
+ return 0xffffffff;
+ if (pciDevNum == SELF) { /* configure our configuration space. */
+ pciDevNum =
+ (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
+ 0x1f;
+ busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
+ 0xff0000;
+ }
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xfc;
+ DataForAddrReg =
+ (regOffset | pciDevNum | functionNum | busNum) | BIT31;
+ GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
+ GT_REG_READ (pci_configuration_address[host], &data);
+ if (data != DataForAddrReg)
+ return 0xffffffff;
+ GT_REG_READ (pci_configuration_data[host], &data);
+ return data;
}
/********************************************************************
@@ -161,37 +182,32 @@
* PCI spec referring to P2P.
*
*********************************************************************/
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum,unsigned int data)
+void pciOverBridgeWriteConfigReg (PCI_HOST host,
+ unsigned int regOffset,
+ unsigned int pciDevNum,
+ unsigned int busNum, unsigned int data)
{
- unsigned int DataForReg;
- unsigned int functionNum;
+ unsigned int DataForReg;
+ unsigned int functionNum;
+
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xff;
+ busNum = busNum << 16;
+ if (pciDevNum == SELF) { /* This board */
+ DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
+ } else {
+ DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+ BIT31 | BIT0;
+ }
+ GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+ if (pciDevNum == SELF) { /* This board */
+ GT_REG_WRITE (pci_configuration_data[host], data);
+ } else { /* configuration Transaction over the pci. */
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if(pciDevNum == SELF) /* This board */
- {
- DataForReg = ( regOffset | pciDevNum | functionNum) | BIT0;
- }
- else
- {
- DataForReg = ( regOffset | pciDevNum | functionNum | busNum) |
- BIT31 | BIT0;
- }
- GT_REG_WRITE(pci_configuration_address[host],DataForReg);
- if(pciDevNum == SELF) /* This board */
- {
- GT_REG_WRITE(pci_configuration_data[host],data);
- }
- else /* configuration Transaction over the pci. */
- {
- /* The PCI is working in LE Mode So it swap the Data. */
- GT_REG_WRITE(pci_configuration_data[host],WORD_SWAP(data));
- }
+ /* The PCI is working in LE Mode So it swap the Data. */
+ GT_REG_WRITE (pci_configuration_data[host], WORD_SWAP (data));
+ }
}
@@ -216,39 +232,35 @@
* |Enable| |Number|Number| Number | Number | | <=field Name
*
*********************************************************************/
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
- unsigned int regOffset,
- unsigned int pciDevNum,
- unsigned int busNum)
+unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
+ unsigned int regOffset,
+ unsigned int pciDevNum,
+ unsigned int busNum)
{
- unsigned int DataForReg;
- unsigned int data;
- unsigned int functionNum;
+ unsigned int DataForReg;
+ unsigned int data;
+ unsigned int functionNum;
- functionNum = regOffset & 0x00000700;
- pciDevNum = pciDevNum << 11;
- regOffset = regOffset & 0xff;
- busNum = busNum << 16;
- if (pciDevNum == SELF) /* This board */
- {
- DataForReg = (regOffset | pciDevNum | functionNum) | BIT31 ;
- }
- else /* agent on another bus */
- {
- DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
- BIT0 | BIT31 ;
- }
- GT_REG_WRITE(pci_configuration_address[host],DataForReg);
- if (pciDevNum == SELF) /* This board */
- {
- GT_REG_READ(pci_configuration_data[host], &data);
- return data;
- }
- else /* The PCI is working in LE Mode So it swap the Data. */
- {
- GT_REG_READ(pci_configuration_data[host], &data);
- return WORD_SWAP(data);
- }
+ functionNum = regOffset & 0x00000700;
+ pciDevNum = pciDevNum << 11;
+ regOffset = regOffset & 0xff;
+ busNum = busNum << 16;
+ if (pciDevNum == SELF) { /* This board */
+ DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
+ } else { /* agent on another bus */
+
+ DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
+ BIT0 | BIT31;
+ }
+ GT_REG_WRITE (pci_configuration_address[host], DataForReg);
+ if (pciDevNum == SELF) { /* This board */
+ GT_REG_READ (pci_configuration_data[host], &data);
+ return data;
+ } else { /* The PCI is working in LE Mode So it swap the Data. */
+
+ GT_REG_READ (pci_configuration_data[host], &data);
+ return WORD_SWAP (data);
+ }
}
/********************************************************************
@@ -258,95 +270,117 @@
* OUTPUT: N/A
* RETURNS: PCI register base address
*********************************************************************/
-static unsigned int pciGetRegOffset(PCI_HOST host, PCI_REGION region)
+static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
{
- switch (host)
- {
+ switch (host) {
case PCI_HOST0:
- switch(region) {
- case PCI_IO: return PCI_0I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0: return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1: return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2: return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3: return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
- }
+ switch (region) {
+ case PCI_IO:
+ return PCI_0I_O_LOW_DECODE_ADDRESS;
+ case PCI_REGION0:
+ return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+ case PCI_REGION1:
+ return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
+ case PCI_REGION2:
+ return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
+ case PCI_REGION3:
+ return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
+ }
case PCI_HOST1:
- switch(region) {
- case PCI_IO: return PCI_1I_O_LOW_DECODE_ADDRESS;
- case PCI_REGION0: return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
- case PCI_REGION1: return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
- case PCI_REGION2: return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
- case PCI_REGION3: return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
- }
- }
- return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
+ switch (region) {
+ case PCI_IO:
+ return PCI_1I_O_LOW_DECODE_ADDRESS;
+ case PCI_REGION0:
+ return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
+ case PCI_REGION1:
+ return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
+ case PCI_REGION2:
+ return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
+ case PCI_REGION3:
+ return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
+ }
+ }
+ return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
}
-static unsigned int pciGetRemapOffset(PCI_HOST host, PCI_REGION region)
+static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
{
- switch (host)
- {
+ switch (host) {
case PCI_HOST0:
- switch(region) {
- case PCI_IO: return PCI_0I_O_ADDRESS_REMAP;
- case PCI_REGION0: return PCI_0MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1: return PCI_0MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2: return PCI_0MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3: return PCI_0MEMORY3_ADDRESS_REMAP;
- }
+ switch (region) {
+ case PCI_IO:
+ return PCI_0I_O_ADDRESS_REMAP;
+ case PCI_REGION0:
+ return PCI_0MEMORY0_ADDRESS_REMAP;
+ case PCI_REGION1:
+ return PCI_0MEMORY1_ADDRESS_REMAP;
+ case PCI_REGION2:
+ return PCI_0MEMORY2_ADDRESS_REMAP;
+ case PCI_REGION3:
+ return PCI_0MEMORY3_ADDRESS_REMAP;
+ }
case PCI_HOST1:
- switch(region) {
- case PCI_IO: return PCI_1I_O_ADDRESS_REMAP;
- case PCI_REGION0: return PCI_1MEMORY0_ADDRESS_REMAP;
- case PCI_REGION1: return PCI_1MEMORY1_ADDRESS_REMAP;
- case PCI_REGION2: return PCI_1MEMORY2_ADDRESS_REMAP;
- case PCI_REGION3: return PCI_1MEMORY3_ADDRESS_REMAP;
- }
- }
- return PCI_0MEMORY0_ADDRESS_REMAP;
+ switch (region) {
+ case PCI_IO:
+ return PCI_1I_O_ADDRESS_REMAP;
+ case PCI_REGION0:
+ return PCI_1MEMORY0_ADDRESS_REMAP;
+ case PCI_REGION1:
+ return PCI_1MEMORY1_ADDRESS_REMAP;
+ case PCI_REGION2:
+ return PCI_1MEMORY2_ADDRESS_REMAP;
+ case PCI_REGION3:
+ return PCI_1MEMORY3_ADDRESS_REMAP;
+ }
+ }
+ return PCI_0MEMORY0_ADDRESS_REMAP;
}
-bool pciMapSpace(PCI_HOST host, PCI_REGION region, unsigned int remapBase, unsigned int bankBase,unsigned int bankLength)
+bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
+ unsigned int bankBase, unsigned int bankLength)
{
- unsigned int low=0xfff;
- unsigned int high=0x0;
- unsigned int regOffset=pciGetRegOffset(host, region);
- unsigned int remapOffset=pciGetRemapOffset(host, region);
+ unsigned int low = 0xfff;
+ unsigned int high = 0x0;
+ unsigned int regOffset = pciGetRegOffset (host, region);
+ unsigned int remapOffset = pciGetRemapOffset (host, region);
- if(bankLength!=0) {
- low = (bankBase >> 20) & 0xfff;
- high=((bankBase+bankLength)>>20)-1;
- }
+ if (bankLength != 0) {
+ low = (bankBase >> 20) & 0xfff;
+ high = ((bankBase + bankLength) >> 20) - 1;
+ }
- GT_REG_WRITE(regOffset, low | (1<<24)); /* no swapping */
- GT_REG_WRITE(regOffset+8, high);
+ GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
+ GT_REG_WRITE (regOffset + 8, high);
- if(bankLength!=0) { /* must do AFTER writing maps */
- GT_REG_WRITE(remapOffset, remapBase>>20); /* sorry, 32 bits only.
- dont support upper 32
- in this driver */
- }
- return true;
+ if (bankLength != 0) { /* must do AFTER writing maps */
+ GT_REG_WRITE (remapOffset, remapBase >> 20); /* sorry, 32 bits only.
+ dont support upper 32
+ in this driver */
+ }
+ return true;
}
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region)
+unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
{
- unsigned int low;
- unsigned int regOffset=pciGetRegOffset(host, region);
- GT_REG_READ(regOffset,&low);
- return (low&0xfff)<<20;
+ unsigned int low;
+ unsigned int regOffset = pciGetRegOffset (host, region);
+
+ GT_REG_READ (regOffset, &low);
+ return (low & 0xfff) << 20;
}
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region)
+unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
{
- unsigned int low,high;
- unsigned int regOffset=pciGetRegOffset(host, region);
- GT_REG_READ(regOffset,&low);
- GT_REG_READ(regOffset+8,&high);
- high&=0xfff;
- low&=0xfff;
- if(high<=low) return 0;
- return (high+1-low)<<20;
+ unsigned int low, high;
+ unsigned int regOffset = pciGetRegOffset (host, region);
+
+ GT_REG_READ (regOffset, &low);
+ GT_REG_READ (regOffset + 8, &high);
+ high &= 0xfff;
+ low &= 0xfff;
+ if (high <= low)
+ return 0;
+ return (high + 1 - low) << 20;
}
/********************************************************************
@@ -354,15 +388,19 @@
*
* Inputs: base and size of PCI SCS
*********************************************************************/
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank, unsigned int pciDramBase,unsigned int pciDramSize)
+void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
+ unsigned int pciDramBase, unsigned int pciDramSize)
{
pciDramBase = pciDramBase & 0xfffff000;
- pciDramBase = pciDramBase | (pciReadConfigReg(host,
- PCI_SCS_0_BASE_ADDRESS + 4*bank,SELF) & 0x00000fff);
- pciWriteConfigReg(host,PCI_SCS_0_BASE_ADDRESS + 4*bank,SELF,pciDramBase);
- if(pciDramSize == 0)
- pciDramSize ++;
- GT_REG_WRITE(pci_scs_bank_size[host][bank], pciDramSize-1);
+ pciDramBase = pciDramBase | (pciReadConfigReg (host,
+ PCI_SCS_0_BASE_ADDRESS
+ + 4 * bank,
+ SELF) & 0x00000fff);
+ pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + 4 * bank, SELF,
+ pciDramBase);
+ if (pciDramSize == 0)
+ pciDramSize++;
+ GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
}
@@ -377,31 +415,33 @@
* unsigned int topAddress - The region top Address.
* Returns: false if one of the parameters is erroneous true otherwise.
*********************************************************************/
-bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,unsigned int features,
- unsigned int baseAddress,unsigned int regionLength)
+bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
+ unsigned int features, unsigned int baseAddress,
+ unsigned int regionLength)
{
- unsigned int accessLow;
- unsigned int accessHigh;
- unsigned int accessTop = baseAddress + regionLength;
+ unsigned int accessLow;
+ unsigned int accessHigh;
+ unsigned int accessTop = baseAddress + regionLength;
- if(regionLength == 0) /* close the region. */
- {
- pciDisableAccessRegion(host, region);
- return true;
- }
- /* base Address is store is bits [11:0] */
- accessLow = (baseAddress & 0xfff00000) >> 20;
- /* All the features are update according to the defines in pci.h (to be on
- the safe side we disable bits: [11:0] */
- accessLow = accessLow | (features & 0xfffff000);
- /* write to the Low Access Region register */
- GT_REG_WRITE( pci_access_control_base_0_low[host] + 0x10*region,accessLow);
+ if (regionLength == 0) { /* close the region. */
+ pciDisableAccessRegion (host, region);
+ return true;
+ }
+ /* base Address is store is bits [11:0] */
+ accessLow = (baseAddress & 0xfff00000) >> 20;
+ /* All the features are update according to the defines in pci.h (to be on
+ the safe side we disable bits: [11:0] */
+ accessLow = accessLow | (features & 0xfffff000);
+ /* write to the Low Access Region register */
+ GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+ accessLow);
- accessHigh = (accessTop & 0xfff00000) >> 20;
+ accessHigh = (accessTop & 0xfff00000) >> 20;
- /* write to the High Access Region register */
- GT_REG_WRITE(pci_access_control_top_0[host] + 0x10*region,accessHigh - 1);
- return true;
+ /* write to the High Access Region register */
+ GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
+ accessHigh - 1);
+ return true;
}
/********************************************************************
@@ -411,11 +451,12 @@
* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
* Returns: N/A.
*********************************************************************/
-void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region)
+void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
{
- /* writing back the registers default values. */
- GT_REG_WRITE(pci_access_control_base_0_low[host] + 0x10*region,0x01001fff);
- GT_REG_WRITE(pci_access_control_top_0[host] + 0x10*region,0);
+ /* writing back the registers default values. */
+ GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
+ 0x01001fff);
+ GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
}
/********************************************************************
@@ -424,13 +465,13 @@
* Inputs: N/A
* Returns: true.
*********************************************************************/
-bool pciArbiterEnable(PCI_HOST host)
+bool pciArbiterEnable (PCI_HOST host)
{
- unsigned int regData;
+ unsigned int regData;
- GT_REG_READ(pci_arbiter_control[host],®Data);
- GT_REG_WRITE(pci_arbiter_control[host],regData | BIT31);
- return true;
+ GT_REG_READ (pci_arbiter_control[host], ®Data);
+ GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
+ return true;
}
/********************************************************************
@@ -439,13 +480,13 @@
* Inputs: N/A
* Returns: true
*********************************************************************/
-bool pciArbiterDisable(PCI_HOST host)
+bool pciArbiterDisable (PCI_HOST host)
{
- unsigned int regData;
+ unsigned int regData;
- GT_REG_READ(pci_arbiter_control[host],®Data);
- GT_REG_WRITE(pci_arbiter_control[host],regData & 0x7fffffff);
- return true;
+ GT_REG_READ (pci_arbiter_control[host], ®Data);
+ GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
+ return true;
}
/********************************************************************
@@ -463,7 +504,7 @@
* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
* Returns: true
*********************************************************************/
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
@@ -471,17 +512,17 @@
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5)
{
- unsigned int regData;
- unsigned int writeData;
+ unsigned int regData;
+ unsigned int writeData;
- GT_REG_READ(pci_arbiter_control[host],®Data);
- writeData = (internalAgent << 14) + (externalAgent0 << 15) + \
- (externalAgent1 << 16) + (externalAgent2 << 17) + \
- (externalAgent3 << 18) + (externalAgent4 << 19) + \
+ GT_REG_READ (pci_arbiter_control[host], ®Data);
+ writeData = (internalAgent << 14) + (externalAgent0 << 15) +
+ (externalAgent1 << 16) + (externalAgent2 << 17) +
+ (externalAgent3 << 18) + (externalAgent4 << 19) +
(externalAgent5 << 20);
- regData = (regData & ~(0x7f<<14)) | writeData;
- GT_REG_WRITE(pci_arbiter_control[host],regData);
- return true;
+ regData = (regData & ~(0x7f << 14)) | writeData;
+ GT_REG_WRITE (pci_arbiter_control[host], regData);
+ return true;
}
/********************************************************************
@@ -497,65 +538,66 @@
* regionLength - Region length.
* Returns: false if one of the parameters is wrong otherwise return true.
*********************************************************************/
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,PCI_SNOOP_TYPE snoopType,
+bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
+ PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength)
{
- unsigned int snoopXbaseAddress;
- unsigned int snoopXtopAddress;
- unsigned int data;
- unsigned int snoopHigh = baseAddress + regionLength;
+ unsigned int snoopXbaseAddress;
+ unsigned int snoopXtopAddress;
+ unsigned int data;
+ unsigned int snoopHigh = baseAddress + regionLength;
- if( (region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB) )
- return false;
- snoopXbaseAddress = pci_snoop_control_base_0_low[host] + 0x10 * region;
- snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
- if(regionLength == 0) /* closing the region */
- {
- GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
- GT_REG_WRITE(snoopXtopAddress,0);
+ if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
+ return false;
+ snoopXbaseAddress =
+ pci_snoop_control_base_0_low[host] + 0x10 * region;
+ snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
+ if (regionLength == 0) { /* closing the region */
+ GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
+ GT_REG_WRITE (snoopXtopAddress, 0);
+ return true;
+ }
+ baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
+ data = (baseAddress >> 20) | snoopType << 12;
+ GT_REG_WRITE (snoopXbaseAddress, data);
+ snoopHigh = (snoopHigh & 0xfff00000) >> 20;
+ GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
return true;
- }
- baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
- data = (baseAddress >> 20) | snoopType << 12;
- GT_REG_WRITE(snoopXbaseAddress,data);
- snoopHigh = (snoopHigh & 0xfff00000) >> 20;
- GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
- return true;
}
/*
*
*/
-static int gt_read_config_dword(struct pci_controller *hose,
- pci_dev_t dev,
- int offset, u32* value)
+static int gt_read_config_dword (struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 * value)
{
- int bus = PCI_BUS(dev);
+ int bus = PCI_BUS (dev);
- if ((bus == local_buses[0]) || (bus == local_buses[1])){
- *value = pciReadConfigReg((PCI_HOST) hose->cfg_addr, offset,
- PCI_DEV(dev));
+ if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+ *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+ PCI_DEV (dev));
} else {
- *value = pciOverBridgeReadConfigReg((PCI_HOST) hose->cfg_addr,
- offset, PCI_DEV(dev), bus);
+ *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
+ cfg_addr, offset,
+ PCI_DEV (dev), bus);
}
return 0;
}
-static int gt_write_config_dword(struct pci_controller *hose,
- pci_dev_t dev,
- int offset, u32 value)
+static int gt_write_config_dword (struct pci_controller *hose,
+ pci_dev_t dev, int offset, u32 value)
{
- int bus = PCI_BUS(dev);
+ int bus = PCI_BUS (dev);
- if ((bus == local_buses[0]) || (bus == local_buses[1])){
- pciWriteConfigReg((PCI_HOST)hose->cfg_addr, offset,
- PCI_DEV(dev), value);
+ if ((bus == local_buses[0]) || (bus == local_buses[1])) {
+ pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
+ PCI_DEV (dev), value);
} else {
- pciOverBridgeWriteConfigReg((PCI_HOST)hose->cfg_addr, offset,
- PCI_DEV(dev), value, bus);
+ pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
+ offset, PCI_DEV (dev), value,
+ bus);
}
return 0;
}
@@ -564,147 +606,145 @@
*
*/
-static void gt_setup_ide(struct pci_controller *hose,
- pci_dev_t dev, struct pci_config_table *entry)
+static void gt_setup_ide (struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *entry)
{
- static const int ide_bar[]={8,4,8,4,0,0};
- u32 bar_response, bar_value;
- int bar;
+ static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
+ u32 bar_response, bar_value;
+ int bar;
- for (bar=0; bar<6; bar++)
- {
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, 0x0);
- pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, &bar_response);
+ for (bar = 0; bar < 6; bar++) {
+ pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ 0x0);
+ pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ &bar_response);
- pciauto_region_allocate(bar_response & PCI_BASE_ADDRESS_SPACE_IO ?
- hose->pci_io : hose->pci_mem, ide_bar[bar], &bar_value);
+ pciauto_region_allocate (bar_response &
+ PCI_BASE_ADDRESS_SPACE_IO ? hose->
+ pci_io : hose->pci_mem, ide_bar[bar],
+ &bar_value);
- pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + bar*4, bar_value);
- }
+ pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ bar_value);
+ }
}
-static void gt_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
{
- unsigned char pin, irq;
+ unsigned char pin, irq;
- pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+ pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
- if(pin == 1) { /* only allow INT A */
- irq = pci_irq_swizzle[(PCI_HOST)hose->cfg_addr][PCI_DEV(dev)];
- if(irq)
- pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
- }
+ if (pin == 1) { /* only allow INT A */
+ irq = pci_irq_swizzle[(PCI_HOST) hose->
+ cfg_addr][PCI_DEV (dev)];
+ if (irq)
+ pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
+ }
}
struct pci_config_table gt_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
- PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
+ {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
- { }
+ {}
};
struct pci_controller pci0_hose = {
- fixup_irq: gt_fixup_irq,
- config_table: gt_config_table,
+ fixup_irq:gt_fixup_irq,
+ config_table:gt_config_table,
};
struct pci_controller pci1_hose = {
- fixup_irq: gt_fixup_irq,
- config_table: gt_config_table,
+ fixup_irq:gt_fixup_irq,
+ config_table:gt_config_table,
};
-void
-pci_init_board(void)
+void pci_init_board (void)
{
- unsigned int command;
+ unsigned int command;
- pci0_hose.first_busno = 0;
- pci0_hose.last_busno = 0xff;
- local_buses[0] = pci0_hose.first_busno;
- /* PCI memory space */
- pci_set_region(pci0_hose.regions + 0,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_MEM_SIZE,
- PCI_REGION_MEM);
+ pci0_hose.first_busno = 0;
+ pci0_hose.last_busno = 0xff;
+ local_buses[0] = pci0_hose.first_busno;
+ /* PCI memory space */
+ pci_set_region (pci0_hose.regions + 0,
+ CFG_PCI0_0_MEM_SPACE,
+ CFG_PCI0_0_MEM_SPACE,
+ CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
- /* PCI I/O space */
- pci_set_region(pci0_hose.regions + 1,
- CFG_PCI0_IO_SPACE_PCI,
- CFG_PCI0_IO_SPACE,
- CFG_PCI0_IO_SIZE,
- PCI_REGION_IO);
+ /* PCI I/O space */
+ pci_set_region (pci0_hose.regions + 1,
+ CFG_PCI0_IO_SPACE_PCI,
+ CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
- pci_set_ops(&pci0_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
+ pci_set_ops (&pci0_hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ gt_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ gt_write_config_dword);
- pci0_hose.region_count = 2;
+ pci0_hose.region_count = 2;
- pci0_hose.cfg_addr = (unsigned int*) PCI_HOST0;
+ pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
- pci_register_hose(&pci0_hose);
+ pci_register_hose (&pci0_hose);
- pciArbiterEnable(PCI_HOST0);
- pciParkingDisable(PCI_HOST0,1,1,1,1,1,1,1);
+ pciArbiterEnable (PCI_HOST0);
+ pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg(PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg(PCI_HOST0, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- pci0_hose.last_busno = pci_hose_scan(&pci0_hose);
+ pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
- command = pciReadConfigReg(PCI_HOST0, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg(PCI_HOST0, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
- pci1_hose.first_busno = pci0_hose.last_busno + 1;
- pci1_hose.last_busno = 0xff;
- pci1_hose.current_busno = pci0_hose.current_busno;
- local_buses[1] = pci1_hose.first_busno;
+ pci1_hose.first_busno = pci0_hose.last_busno + 1;
+ pci1_hose.last_busno = 0xff;
+ pci1_hose.current_busno = pci0_hose.current_busno;
+ local_buses[1] = pci1_hose.first_busno;
- /* PCI memory space */
- pci_set_region(pci1_hose.regions + 0,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
+ /* PCI memory space */
+ pci_set_region (pci1_hose.regions + 0,
+ CFG_PCI1_0_MEM_SPACE,
+ CFG_PCI1_0_MEM_SPACE,
+ CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
- /* PCI I/O space */
- pci_set_region(pci1_hose.regions + 1,
- CFG_PCI1_IO_SPACE_PCI,
- CFG_PCI1_IO_SPACE,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
+ /* PCI I/O space */
+ pci_set_region (pci1_hose.regions + 1,
+ CFG_PCI1_IO_SPACE_PCI,
+ CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
- pci_set_ops(&pci1_hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- gt_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- gt_write_config_dword);
+ pci_set_ops (&pci1_hose,
+ pci_hose_read_config_byte_via_dword,
+ pci_hose_read_config_word_via_dword,
+ gt_read_config_dword,
+ pci_hose_write_config_byte_via_dword,
+ pci_hose_write_config_word_via_dword,
+ gt_write_config_dword);
- pci1_hose.region_count = 2;
+ pci1_hose.region_count = 2;
- pci1_hose.cfg_addr = (unsigned int*) PCI_HOST1;
+ pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
- pci_register_hose(&pci1_hose);
+ pci_register_hose (&pci1_hose);
- pciArbiterEnable(PCI_HOST1);
- pciParkingDisable(PCI_HOST1,1,1,1,1,1,1,1);
+ pciArbiterEnable (PCI_HOST1);
+ pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
- command = pciReadConfigReg(PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MASTER;
- pciWriteConfigReg(PCI_HOST1, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MASTER;
+ pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
- pci1_hose.last_busno = pci_hose_scan(&pci1_hose);
+ pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
- command = pciReadConfigReg(PCI_HOST1, PCI_COMMAND, SELF);
- command |= PCI_COMMAND_MEMORY;
- pciWriteConfigReg(PCI_HOST1, PCI_COMMAND, SELF, command);
+ command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
+ command |= PCI_COMMAND_MEMORY;
+ pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
}
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
index d019d22..d9318d5 100644
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -54,65 +54,64 @@
uchar tras_clocks;
uchar burst_len;
uchar banks, slot;
- int size; /* detected size, not from I2C but from dram_size() */
+ int size; /* detected size, not from I2C but from dram_size() */
} sdram_info_t;
#ifdef DEBUG
-void dump_dimm_info(struct sdram_info *d)
+void dump_dimm_info (struct sdram_info *d)
{
- static const char *ecc_legend[]={""," Parity"," ECC"};
- printf("dimm%s %sDRAM: %dMibytes:\n",
- ecc_legend[d->ecc],
- d->registered?"R":"",
- (d->size>>20));
- printf(" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
- d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
- d->banks, d->slot);
+ static const char *ecc_legend[] = { "", " Parity", " ECC" };
+
+ printf ("dimm%s %sDRAM: %dMibytes:\n",
+ ecc_legend[d->ecc],
+ d->registered ? "R" : "", (d->size >> 20));
+ printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
+ d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
+ d->banks, d->slot);
}
#endif
static int
-memory_map_bank(unsigned int bankNo,
- unsigned int bankBase,
- unsigned int bankLength)
+memory_map_bank (unsigned int bankNo,
+ unsigned int bankBase, unsigned int bankLength)
{
#ifdef DEBUG
if (bankLength > 0) {
- printf("mapping bank %d at %08x - %08x\n",
- bankNo, bankBase, bankBase + bankLength - 1);
+ printf ("mapping bank %d at %08x - %08x\n",
+ bankNo, bankBase, bankBase + bankLength - 1);
} else {
- printf("unmapping bank %d\n", bankNo);
+ printf ("unmapping bank %d\n", bankNo);
}
#endif
- memoryMapBank(bankNo, bankBase, bankLength);
+ memoryMapBank (bankNo, bankBase, bankLength);
return 0;
}
#ifdef MAP_PCI
static int
-memory_map_bank_pci(unsigned int bankNo,
- unsigned int bankBase,
- unsigned int bankLength)
+memory_map_bank_pci (unsigned int bankNo,
+ unsigned int bankBase, unsigned int bankLength)
{
PCI_HOST host;
- for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
- const int features=
+
+ for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
+ const int features =
PREFETCH_ENABLE |
DELAYED_READ_ENABLE |
AGGRESSIVE_PREFETCH |
READ_LINE_AGGRESSIVE_PREFETCH |
READ_MULTI_AGGRESSIVE_PREFETCH |
- MAX_BURST_4 |
- PCI_NO_SWAP;
+ MAX_BURST_4 | PCI_NO_SWAP;
- pciMapMemoryBank(host, bankNo, bankBase, bankLength);
+ pciMapMemoryBank (host, bankNo, bankBase, bankLength);
- pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
- bankLength);
+ pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
+ bankLength);
- pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
+ pciSetRegionFeatures (host, bankNo, features, bankBase,
+ bankLength);
}
return 0;
}
@@ -128,8 +127,7 @@
* translate ns.ns/10 coding of SPD timing values
* into 10 ps unit values
*/
-static inline unsigned short
-NS10to10PS(unsigned char spd_byte)
+static inline unsigned short NS10to10PS (unsigned char spd_byte)
{
unsigned short ns, ns10;
@@ -138,37 +136,35 @@
/* isolate lower nibble */
ns10 = (spd_byte & 0x0F);
- return(ns*100 + ns10*10);
+ return (ns * 100 + ns10 * 10);
}
/*
* translate ns coding of SPD timing values
* into 10 ps unit values
*/
-static inline unsigned short
-NSto10PS(unsigned char spd_byte)
+static inline unsigned short NSto10PS (unsigned char spd_byte)
{
- return(spd_byte*100);
+ return (spd_byte * 100);
}
#ifdef CONFIG_ZUMA_V2
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
{
/* assume 2 dimms, 2 banks each 256M - we dont have an
* dimm i2c so rely on the detection routines later */
- memset(info, 0, sizeof(*info));
+ memset (info, 0, sizeof (*info));
info->slot = slot;
info->banks = 2; /* Detect later */
- info->registered = 0;
+ info->registered = 0;
info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
but doesn't matter, both do same
thing in setup_sdram() */
- info->tpar = 3;
- info->tras_clocks = 5;
- info->burst_len = 4;
+ info->tpar = 3;
+ info->tras_clocks = 5;
+ info->burst_len = 4;
#ifdef CONFIG_ECC
info->ecc = 0; /* Detect later */
#endif /* CONFIG_ECC */
@@ -177,10 +173,9 @@
#elif defined(CONFIG_P3G4)
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
{
- memset(info, 0, sizeof(*info));
+ memset (info, 0, sizeof (*info));
if (slot)
return 0;
@@ -198,12 +193,11 @@
return 0;
}
-#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4*/
+#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
/* This code reads the SPD chip on the sdram and populates
* the array which is passed in with the relevant information */
-static int
-check_dimm(uchar slot, sdram_info_t *info)
+static int check_dimm (uchar slot, sdram_info_t * info)
{
DECLARE_GLOBAL_DATA_PTR;
uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
@@ -215,32 +209,32 @@
get_clocks ();
- tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
+ tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
#ifdef CONFIG_EVB64260_750CX
if (0 != slot) {
- printf("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
- printf(" called with slot=%d insetad!\n", slot);
+ printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
+ printf (" called with slot=%d insetad!\n", slot);
return 0;
}
#endif
- DP(puts("before i2c read\n"));
+ DP (puts ("before i2c read\n"));
- ret = i2c_read(addr, 0, 128, data, 0);
+ ret = i2c_read (addr, 0, 128, data, 0);
- DP(puts("after i2c read\n"));
+ DP (puts ("after i2c read\n"));
/* zero all the values */
- memset(info, 0, sizeof(*info));
+ memset (info, 0, sizeof (*info));
if (ret) {
- DP(printf("No DIMM in slot %d [err = %x]\n", slot, ret));
+ DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
return 0;
}
/* first, do some sanity checks */
if (data[2] != 0x4) {
- printf("Not SDRAM in slot %d\n", slot);
+ printf ("Not SDRAM in slot %d\n", slot);
return 0;
}
@@ -251,7 +245,8 @@
sdram_banks = data[17];
width = data[13] & 0x7f;
- DP(printf("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
+ DP (printf
+ ("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
/* check if the memory is registered */
if (data[21] & (BIT1 | BIT4))
@@ -266,31 +261,31 @@
supp_cal = (data[18] & 0x6) >> 1;
/* compute the relevant clock values */
- trp_clocks = (NSto10PS(data[27])+(tmemclk-1)) / tmemclk;
- trcd_clocks = (NSto10PS(data[29])+(tmemclk-1)) / tmemclk;
- info->tras_clocks = (NSto10PS(data[30])+(tmemclk-1)) / tmemclk;
+ trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
+ trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
+ info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
- DP(printf("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
- trp_clocks, trcd_clocks, info->tras_clocks));
+ DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
+ trp_clocks, trcd_clocks, info->tras_clocks));
/* try a CAS latency of 3 first... */
cal_val = 0;
if (supp_cal & 3) {
- if (NS10to10PS(data[9]) <= tmemclk)
+ if (NS10to10PS (data[9]) <= tmemclk)
cal_val = 3;
}
/* then 2... */
if (supp_cal & 2) {
- if (NS10to10PS(data[23]) <= tmemclk)
+ if (NS10to10PS (data[23]) <= tmemclk)
cal_val = 2;
}
- DP(printf("cal_val = %d\n", cal_val));
+ DP (printf ("cal_val = %d\n", cal_val));
/* bummer, did't work... */
if (cal_val == 0) {
- DP(printf("Couldn't find a good CAS latency\n"));
+ DP (printf ("Couldn't find a good CAS latency\n"));
return 0;
}
@@ -302,18 +297,19 @@
if (trcd_clocks > info->tpar)
info->tpar = trcd_clocks;
- DP(printf("tpar set to: %d\n", info->tpar));
+ DP (printf ("tpar set to: %d\n", info->tpar));
#ifdef CFG_BROKEN_CL2
- if (info->tpar == 2){
+ if (info->tpar == 2) {
info->tpar = 3;
- DP(printf("tpar fixed-up to: %d\n", info->tpar));
+ DP (printf ("tpar fixed-up to: %d\n", info->tpar));
}
#endif
/* compute the module DRB size */
- info->drb_size = (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
+ info->drb_size =
+ (((1 << (rows + cols)) * sdram_banks) * width) / _16M;
- DP(printf("drb_size set to: %d\n", info->drb_size));
+ DP (printf ("drb_size set to: %d\n", info->drb_size));
/* find the burst len */
info->burst_len = data[16] & 0xf;
@@ -330,40 +326,52 @@
}
#endif /* ! CONFIG_ZUMA_V2 */
-static int
-setup_sdram_common(sdram_info_t info[2])
+static int setup_sdram_common (sdram_info_t info[2])
{
ulong tmp;
- int tpar=2, tras_clocks=5, registered=1, ecc=2;
+ int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
- if(!info[0].banks && !info[1].banks) return 0;
+ if (!info[0].banks && !info[1].banks)
+ return 0;
+
+ if (info[0].banks) {
+ if (info[0].tpar > tpar)
+ tpar = info[0].tpar;
+ if (info[0].tras_clocks > tras_clocks)
+ tras_clocks = info[0].tras_clocks;
+ if (!info[0].registered)
+ registered = 0;
+ if (info[0].ecc != 2indent: Standard input:491: Warning:old style assignment ambiguity in "=*". Assuming "= *"
+
+indent: Standard input:492: Warning:old style assignment ambiguity in "=*". Assuming "= *"
- if(info[0].banks) {
- if(info[0].tpar>tpar) tpar=info[0].tpar;
- if(info[0].tras_clocks>tras_clocks) tras_clocks=info[0].tras_clocks;
- if(!info[0].registered) registered=0;
- if(info[0].ecc!=2) ecc=0;
+)
+ ecc = 0;
}
- if(info[1].banks) {
- if(info[1].tpar>tpar) tpar=info[1].tpar;
- if(info[1].tras_clocks>tras_clocks) tras_clocks=info[1].tras_clocks;
- if(!info[1].registered) registered=0;
- if(info[1].ecc!=2) ecc=0;
+ if (info[1].banks) {
+ if (info[1].tpar > tpar)
+ tpar = info[1].tpar;
+ if (info[1].tras_clocks > tras_clocks)
+ tras_clocks = info[1].tras_clocks;
+ if (!info[1].registered)
+ registered = 0;
+ if (info[1].ecc != 2)
+ ecc = 0;
}
/* SDRAM configuration */
- tmp = GTREGREAD(SDRAM_CONFIGURATION);
+ tmp = GTREGREAD (SDRAM_CONFIGURATION);
/* Turn on physical interleave if both DIMMs
* have even numbers of banks. */
- if( (info[0].banks == 0 || info[0].banks == 2) &&
- (info[1].banks == 0 || info[1].banks == 2) ) {
- /* physical interleave on */
- tmp &= ~(1 << 15);
+ if ((info[0].banks == 0 || info[0].banks == 2) &&
+ (info[1].banks == 0 || info[1].banks == 2)) {
+ /* physical interleave on */
+ tmp &= ~(1 << 15);
} else {
- /* physical interleave off */
- tmp |= (1 << 15);
+ /* physical interleave off */
+ tmp |= (1 << 15);
}
tmp |= (registered << 17);
@@ -372,52 +380,51 @@
* See Res #12 */
tmp |= (1 << 26);
- GT_REG_WRITE(SDRAM_CONFIGURATION, tmp);
- DP(printf("SDRAM config: %08x\n",
- GTREGREAD(SDRAM_CONFIGURATION)));
+ GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
+ DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
/* SDRAM timing */
tmp = (((tpar == 3) ? 2 : 1) |
(((tpar == 3) ? 2 : 1) << 2) |
- (((tpar == 3) ? 2 : 1) << 4) |
- (tras_clocks << 8));
+ (((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
#ifdef CONFIG_ECC
/* Setup ECC */
- if (ecc == 2) tmp |= 1<<13;
+ if (ecc == 2)
+ tmp |= 1 << 13;
#endif /* CONFIG_ECC */
- GT_REG_WRITE(SDRAM_TIMING, tmp);
- DP(printf("SDRAM timing: %08x (%d,%d,%d,%d)\n",
- GTREGREAD(SDRAM_TIMING), tpar,tpar,tpar,tras_clocks));
+ GT_REG_WRITE (SDRAM_TIMING, tmp);
+ DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
+ GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
/* SDRAM address decode register */
/* program this with the default value */
- GT_REG_WRITE(SDRAM_ADDRESS_DECODE, 0x2);
- DP(printf("SDRAM decode: %08x\n",
- GTREGREAD(SDRAM_ADDRESS_DECODE)));
+ GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
+ DP (printf ("SDRAM decode: %08x\n",
+ GTREGREAD (SDRAM_ADDRESS_DECODE)));
return 0;
}
/* sets up the GT properly with information passed in */
-static int
-setup_sdram(sdram_info_t *info)
+static int setup_sdram (sdram_info_t * info)
{
ulong tmp, check;
ulong *addr = 0;
int i;
/* sanity checking */
- if (! info->banks) return 0;
+ if (!info->banks)
+ return 0;
/* ---------------------------- */
/* Program the GT with the discovered data */
/* bank parameters */
- tmp = (0xf<<16); /* leave all virt bank pages open */
+ tmp = (0xf << 16); /* leave all virt bank pages open */
- DP(printf("drb_size: %d\n", info->drb_size));
+ DP (printf ("drb_size: %d\n", info->drb_size));
switch (info->drb_size) {
case 1:
tmp |= (1 << 14);
@@ -431,41 +438,42 @@
tmp |= (3 << 14);
break;
default:
- printf("Error in dram size calculation\n");
+ printf ("Error in dram size calculation\n");
return 1;
}
/* SDRAM bank parameters */
/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
- GT_REG_WRITE(SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
- GT_REG_WRITE(SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
- DP(printf("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot, info->slot*2, (info->slot*2)+1, tmp));
+ GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
+ GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
+ DP (printf
+ ("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
+ info->slot * 2, (info->slot * 2) + 1, tmp));
/* set the SDRAM configuration for each bank */
for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
- DP(printf("*** Running a MRS cycle for bank %d ***\n", i));
+ DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
/* map the bank */
- memory_map_bank(i, 0, GB/4);
+ memory_map_bank (i, 0, GB / 4);
/* set SDRAM mode */
- GT_REG_WRITE(SDRAM_OPERATION_MODE, 0x3);
- check = GTREGREAD(SDRAM_OPERATION_MODE);
+ GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
+ check = GTREGREAD (SDRAM_OPERATION_MODE);
/* dummy write */
*addr = 0;
/* wait for the command to complete */
- while ((GTREGREAD(SDRAM_OPERATION_MODE) & (1 << 31)) == 0)
- ;
+ while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
/* switch back to normal operation mode */
- GT_REG_WRITE(SDRAM_OPERATION_MODE, 0);
- check = GTREGREAD(SDRAM_OPERATION_MODE);
+ GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
+ check = GTREGREAD (SDRAM_OPERATION_MODE);
/* unmap the bank */
- memory_map_bank(i, 0, 0);
- DP(printf("*** MRS cycle for bank %d done ***\n", i));
+ memory_map_bank (i, 0, 0);
+ DP (printf ("*** MRS cycle for bank %d done ***\n", i));
}
return 0;
@@ -478,50 +486,50 @@
* - short between address lines
* - short between data lines
*/
-static long int
-dram_size(long int *base, long int maxsize)
+static long int dram_size (long int *base, long int maxsize)
{
- volatile long int *addr, *b=base;
- long int cnt, val, save1, save2;
+ volatile long int *addr, *b = base;
+ long int cnt, val, save1, save2;
#define STARTVAL (1<<20) /* start test at 1M */
- for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
+ for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
+ cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
- save1=*addr; /* save contents of addr */
- save2=*b; /* save contents of base */
+ save1 = *addr; /* save contents of addr */
+ save2 = *b; /* save contents of base */
- *addr=cnt; /* write cnt to addr */
- *b=0; /* put null at base */
+ *addr = cnt; /* write cnt to addr */
+ *b = 0; /* put null at base */
- /* check at base address */
- if ((*b) != 0) {
- *addr=save1; /* restore *addr */
- *b=save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
+ /* check at base address */
+ if ((*b) != 0) {
+ *addr = save1; /* restore *addr */
+ *b = save2; /* restore *b */
+ return (0);
+ }
+ val = *addr; /* read *addr */
- *addr=save1;
- *b=save2;
+ *addr = save1;
+ *b = save2;
- if (val != cnt) {
- /* fix boundary condition.. STARTVAL means zero */
- if(cnt==STARTVAL/sizeof(long)) cnt=0;
- return (cnt * sizeof(long));
- }
- }
- return maxsize;
+ if (val != cnt) {
+ /* fix boundary condition.. STARTVAL means zero */
+ if (cnt == STARTVAL / sizeof (long))
+ cnt = 0;
+ return (cnt * sizeof (long));
+ }
+ }
+ return maxsize;
}
/* ------------------------------------------------------------------------- */
/* U-Boot interface function to SDRAM init - this is where all the
* controlling logic happens */
-long int
-initdram(int board_type)
+long int initdram (int board_type)
{
- ulong checkbank[4] = { [0 ... 3] = 0 };
+ ulong checkbank[4] = {[0 ... 3] = 0 };
int bank_no;
ulong total;
int nhr;
@@ -531,92 +539,97 @@
/* first, use the SPD to get info about the SDRAM */
/* check the NHR bit and skip mem init if it's already done */
- nhr = get_hid0() & (1 << 16);
+ nhr = get_hid0 () & (1 << 16);
if (nhr) {
- printf("Skipping SDRAM setup due to NHR bit being set\n");
+ printf ("Skipping SDRAM setup due to NHR bit being set\n");
} else {
/* DIMM0 */
- check_dimm(0, &dimm_info[0]);
+ check_dimm (0, &dimm_info[0]);
/* DIMM1 */
-#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
- check_dimm(1, &dimm_info[1]);
-#else /* CONFIG_EVB64260_750CX */
- memset(&dimm_info[1], 0, sizeof(sdram_info_t));
+#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
+ check_dimm (1, &dimm_info[1]);
+#else /* CONFIG_EVB64260_750CX */
+ memset (&dimm_info[1], 0, sizeof (sdram_info_t));
#endif
/* unmap all banks */
- memory_map_bank(0, 0, 0);
- memory_map_bank(1, 0, 0);
- memory_map_bank(2, 0, 0);
- memory_map_bank(3, 0, 0);
+ memory_map_bank (0, 0, 0);
+ memory_map_bank (1, 0, 0);
+ memory_map_bank (2, 0, 0);
+ memory_map_bank (3, 0, 0);
/* Now, program the GT with the correct values */
- if (setup_sdram_common(dimm_info)) {
- printf("Setup common failed.\n");
+ if (setup_sdram_common (dimm_info)) {
+ printf ("Setup common failed.\n");
}
- if (setup_sdram(&dimm_info[0])) {
- printf("Setup for DIMM1 failed.\n");
+ if (setup_sdram (&dimm_info[0])) {
+ printf ("Setup for DIMM1 failed.\n");
}
- if (setup_sdram(&dimm_info[1])) {
- printf("Setup for DIMM2 failed.\n");
+ if (setup_sdram (&dimm_info[1])) {
+ printf ("Setup for DIMM2 failed.\n");
}
/* set the NHR bit */
- set_hid0(get_hid0() | (1 << 16));
+ set_hid0 (get_hid0 () | (1 << 16));
}
/* next, size the SDRAM banks */
total = 0;
- if (dimm_info[0].banks > 0) checkbank[0] = 1;
- if (dimm_info[0].banks > 1) checkbank[1] = 1;
+ if (dimm_info[0].banks > 0)
+ checkbank[0] = 1;
+ if (dimm_info[0].banks > 1)
+ checkbank[1] = 1;
if (dimm_info[0].banks > 2)
- printf("Error, SPD claims DIMM1 has >2 banks\n");
+ printf ("Error, SPD claims DIMM1 has >2 banks\n");
- if (dimm_info[1].banks > 0) checkbank[2] = 1;
- if (dimm_info[1].banks > 1) checkbank[3] = 1;
+ if (dimm_info[1].banks > 0)
+ checkbank[2] = 1;
+ if (dimm_info[1].banks > 1)
+ checkbank[3] = 1;
if (dimm_info[1].banks > 2)
- printf("Error, SPD claims DIMM2 has >2 banks\n");
+ printf ("Error, SPD claims DIMM2 has >2 banks\n");
/* Generic dram sizer: works even if we don't have i2c DIMMs,
* as long as the timing settings are more or less correct */
/*
* pass 1: size all the banks, using first bat (0-256M)
- * limitation: we only support 256M per bank due to
- * us only having 1 BAT for all DRAM
+ * limitation: we only support 256M per bank due to
+ * us only having 1 BAT for all DRAM
*/
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
/* skip over banks that are not populated */
- if (! checkbank[bank_no])
+ if (!checkbank[bank_no])
continue;
- DP(printf("checking bank %d\n", bank_no));
+ DP (printf ("checking bank %d\n", bank_no));
- memory_map_bank(bank_no, 0, GB/4);
- checkbank[bank_no] = dram_size(NULL, GB/4);
- memory_map_bank(bank_no, 0, 0);
+ memory_map_bank (bank_no, 0, GB / 4);
+ checkbank[bank_no] = dram_size (NULL, GB / 4);
+ memory_map_bank (bank_no, 0, 0);
- DP(printf("bank %d %08lx\n", bank_no, checkbank[bank_no]));
+ DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
}
/*
* pass 2: contiguously map each bank into physical address
- * space.
+ * space.
*/
- dimm_info[0].banks=dimm_info[1].banks=0;
+ dimm_info[0].banks = dimm_info[1].banks = 0;
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
- if(!checkbank[bank_no]) continue;
+ if (!checkbank[bank_no])
+ continue;
- dimm_info[bank_no/2].banks++;
- dimm_info[bank_no/2].size+=checkbank[bank_no];
+ dimm_info[bank_no / 2].banks++;
+ dimm_info[bank_no / 2].size += checkbank[bank_no];
- memory_map_bank(bank_no, total, checkbank[bank_no]);
+ memory_map_bank (bank_no, total, checkbank[bank_no]);
#ifdef MAP_PCI
- memory_map_bank_pci(bank_no, total, checkbank[bank_no]);
+ memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
#endif
total += checkbank[bank_no];
}
@@ -630,21 +643,22 @@
* in that configuration, ECC chips are mounted, even for stacked
* chips)
*/
- if (checkbank[2]==0 && checkbank[3]==0) {
- dimm_info[0].ecc=2;
- GT_REG_WRITE(SDRAM_TIMING, GTREGREAD(SDRAM_TIMING) | (1 << 13));
+ if (checkbank[2] == 0 && checkbank[3] == 0) {
+ dimm_info[0].ecc = 2;
+ GT_REG_WRITE (SDRAM_TIMING,
+ GTREGREAD (SDRAM_TIMING) | (1 << 13));
/* TODO: do we have to run MRS cycles again? */
}
#endif /* CONFIG_ZUMA_V2 */
- if (GTREGREAD(SDRAM_TIMING) & (1 << 13)) {
- puts("[ECC] ");
+ if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
+ puts ("[ECC] ");
}
#endif /* CONFIG_ECC */
#ifdef DEBUG
- dump_dimm_info(&dimm_info[0]);
- dump_dimm_info(&dimm_info[1]);
+ dump_dimm_info (&dimm_info[0]);
+ dump_dimm_info (&dimm_info[1]);
#endif
/* TODO: return at MOST 256M? */
/* return total > GB/4 ? GB/4 : total; */
diff --git a/board/evb64260/zuma_pbb_mbox.h b/board/evb64260/zuma_pbb_mbox.h
index 0e80fcb..b4a4c0c 100644
--- a/board/evb64260/zuma_pbb_mbox.h
+++ b/board/evb64260/zuma_pbb_mbox.h
@@ -2,33 +2,33 @@
#define OUT_PENDING 2
enum {
- ZUMA_MBOXMSG_DONE,
- ZUMA_MBOXMSG_MACL,
- ZUMA_MBOXMSG_MACH,
- ZUMA_MBOXMSG_IP,
- ZUMA_MBOXMSG_SLOT,
- ZUMA_MBOXMSG_RESET,
- ZUMA_MBOXMSG_BAUD,
- ZUMA_MBOXMSG_START,
- ZUMA_MBOXMSG_ENG_PRV_MACL,
- ZUMA_MBOXMSG_ENG_PRV_MACH,
+ ZUMA_MBOXMSG_DONE,
+ ZUMA_MBOXMSG_MACL,
+ ZUMA_MBOXMSG_MACH,
+ ZUMA_MBOXMSG_IP,
+ ZUMA_MBOXMSG_SLOT,
+ ZUMA_MBOXMSG_RESET,
+ ZUMA_MBOXMSG_BAUD,
+ ZUMA_MBOXMSG_START,
+ ZUMA_MBOXMSG_ENG_PRV_MACL,
+ ZUMA_MBOXMSG_ENG_PRV_MACH,
- MBOXMSG_LAST
+ MBOXMSG_LAST
};
struct zuma_mailbox_info {
- unsigned char acc_mac[6];
- unsigned char prv_mac[6];
- unsigned int ip;
- unsigned int slot_bac;
- unsigned int console_baud;
- unsigned int debug_baud;
+ unsigned char acc_mac[6];
+ unsigned char prv_mac[6];
+ unsigned int ip;
+ unsigned int slot_bac;
+ unsigned int console_baud;
+ unsigned int debug_baud;
};
struct _zuma_mbox_dev {
- pci_dev_t dev;
- PBB_DMA_REG_MAP *sip;
- struct zuma_mailbox_info mailbox;
+ pci_dev_t dev;
+ PBB_DMA_REG_MAP *sip;
+ struct zuma_mailbox_info mailbox;
};
#define zuma_prv_mac zuma_mbox_dev.mailbox.prv_mac
@@ -40,4 +40,4 @@
extern struct _zuma_mbox_dev zuma_mbox_dev;
-extern int zuma_mbox_init(void);
+extern int zuma_mbox_init (void);