riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..3402d09 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@
mv sp, a0
#endif
+#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@@ -106,6 +107,9 @@
li s2, 1
amoswap.w s2, t1, 0(t0)
bnez s2, wait_for_gd_init
+#else
+ bnez tp, secondary_hart_loop
+#endif
la t0, prior_stage_fdt_address
SREG s1, 0(t0)
@@ -115,6 +119,7 @@
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
+#ifndef CONFIG_XIP
la t0, available_harts_lock
fence rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,6 +146,7 @@
* secondary_hart_loop.
*/
bnez s2, secondary_hart_loop
+#endif
/* Enable cache */
jal icache_enable