commit e54a67f5e38baebb491ac7a152a6ad77debbaad7
author Matthias Fuchs <matthias.fuchs@esd.eu> Wed Aug 07 12:10:38 2013 +0200
committer Tom Rini <trini@ti.com> Tue Aug 20 11:35:24 2013 -0400
tree ee86943cebf490244fed648f69425438c3c39b95
parent c2e47d2b50835d34056a48a0189025e173d9f4a1

ppc4xx: Remove support for PPC405CR CPUs

This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

arch/powerpc/cpu/ppc4xx/4xx_uart.c

diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
index cad61f3..50c28a0 100644
--- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c
@@ -17,7 +17,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
+#if defined(CONFIG_405GP) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
     defined(CONFIG_405EX) || defined(CONFIG_440)
 
@@ -68,7 +68,7 @@
 #define UDIV_SUBTRACT	0
 #define UART0_SDR	SDR0_UART0
 #define UART1_SDR	SDR0_UART1
-#else /* CONFIG_405GP || CONFIG_405CR */
+#else /* CONFIG_405GP */
 #define CR0_MASK        0x00001fff
 #define CR0_EXTCLK_ENA  0x000000c0
 #define CR0_UDIV_POS    1
@@ -173,7 +173,7 @@
 	 * Let's handle this in some #ifdef's for the SoC's.
 	 */
 
-#if defined(CONFIG_405CR) || defined(CONFIG_405GP)
+#if defined(CONFIG_405GP)
 	reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
@@ -200,7 +200,7 @@
 #else
 	clk = CONFIG_SYS_BASE_BAUD * 16;
 #endif
-#endif /* CONFIG_405CR */
+#endif
 
 #if defined(CONFIG_405EP)
 	{
@@ -265,4 +265,4 @@
 
 	return clk;
 }
-#endif	/* CONFIG_405GP || CONFIG_405CR */
+#endif	/* CONFIG_405GP */