* Patch by Peter Ryser, 20 Feb 2004:
Add support for the Xilinx ML300 platform
* Patch by Stephan Linz, 17 Feb 2004:
Fix watchdog support for NIOS
* Patch by Josh Fryman, 16 Feb 2004:
Fix byte-swapping for cfi_flash.c for different bus widths
* Patch by Jon Diekema, 14 Jeb 2004:
Remove duplicate "FPGA Support" notes from the README file
diff --git a/board/omap1610inn/omap1610innovator.c b/board/omap1610inn/omap1610innovator.c
index 0f67a0c..521eee3 100644
--- a/board/omap1610inn/omap1610innovator.c
+++ b/board/omap1610inn/omap1610innovator.c
@@ -11,7 +11,7 @@
* Kshitij Gupta <Kshitij@ti.com>
*
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -112,9 +112,9 @@
#ifdef CONFIG_H2_OMAP1610
#define LAN_RESET_REGISTER 0x0400001c
- /* The debug board on which the lan chip resides may not be powered
- * ON at the same time as the OMAP chip. So wait in a loop until the
- * lan reset register (on the debug board) is available (powered on)
+ /* The debug board on which the lan chip resides may not be powered
+ * ON at the same time as the OMAP chip. So wait in a loop until the
+ * lan reset register (on the debug board) is available (powered on)
* and reset the lan chip.
*/
@@ -123,7 +123,7 @@
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
udelay (3);
} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
-
+
do {
*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
udelay (3);
diff --git a/board/omap1610inn/platform.S b/board/omap1610inn/platform.S
index 1775695..4d6224c 100644
--- a/board/omap1610inn/platform.S
+++ b/board/omap1610inn/platform.S
@@ -6,7 +6,7 @@
* Kshitij Gupta <Kshitij@ti.com>
*
* Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -251,7 +251,7 @@
ldr r0, REG_TC_EMIFS_CS3_CONFIG
str r1, [r0] /* Chip Select 3 */
-#ifdef CONFIG_H2_OMAP1610
+#ifdef CONFIG_H2_OMAP1610
/* inserting additional 2 clock cycle hold time for LAN */
ldr r0, REG_TC_EMIFS_CS1_ADVANCED
ldr r1, VAL_TC_EMIFS_CS1_ADVANCED