Merge tag 'u-boot-stm32-20200214' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- add DH Electronics DHCOM SoM and PDK2 board
- DT alignment with kernel v5.5-rc7 for stm32mp1 boards
- fix STM32 image format for big endian hosts in mkimage
- solve warnings in device tree and code for stm32mp1 boards
- remove fdt_high and initrd_high for stm32 and stih boards
- add support of STM32MP15x Rev.Z
- update stm32mp1 readme
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4fee5cc..be4cf02 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -882,7 +882,8 @@
stm32mp157a-avenger96.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
- stm32mp157c-ev1.dtb
+ stm32mp157c-ev1.dtb \
+ stm32mp15xx-dhcom-pdk2.dtb
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
index 479b700..38f29bb 100644
--- a/arch/arm/dts/stm32mp15-ddr.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -5,7 +5,7 @@
/ {
soc {
- ddr: ddr@5A003000 {
+ ddr: ddr@5a003000 {
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi
index 0d53396..81a363d 100644
--- a/arch/arm/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi
@@ -138,7 +138,16 @@
status = "disabled";
};
- adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
+ adc12_ain_pins_a: adc12-ain-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
+ <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
+ <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
+ <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
+ };
+ };
+
+ adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
<STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
@@ -175,6 +184,18 @@
};
};
+ dac_ch1_pins_a: dac-ch1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
+ };
+ };
+
+ dac_ch2_pins_a: dac-ch2 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
+ };
+ };
+
dcmi_pins_a: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
@@ -622,13 +643,13 @@
<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
bias-pull-up;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
};
@@ -650,13 +671,13 @@
<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
pins2 {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <1>;
};
};
diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi
index 0d1d387..8f9535a 100644
--- a/arch/arm/dts/stm32mp157-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157-u-boot.dtsi
@@ -128,12 +128,14 @@
u-boot,dm-pre-reloc;
};
-&pwr {
+&pwr_regulators {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
&sdmmc1 {
diff --git a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
index 1104a70..d6dc746 100644
--- a/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-avenger96-u-boot.dtsi
@@ -91,7 +91,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4Q
+ CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
@@ -105,6 +105,8 @@
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
@@ -112,6 +114,8 @@
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
@@ -119,6 +123,8 @@
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
@@ -126,6 +132,8 @@
/* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
cfg = < 1 39 3 11 4 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32mp157a-avenger96.dts b/arch/arm/dts/stm32mp157a-avenger96.dts
index 5b15a4a..3065593 100644
--- a/arch/arm/dts/stm32mp157a-avenger96.dts
+++ b/arch/arm/dts/stm32mp157a-avenger96.dts
@@ -252,14 +252,13 @@
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
interrupt-parent = <&pmic>;
- regulator-active-discharge;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
interrupt-parent = <&pmic>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -282,11 +281,9 @@
status = "okay";
};
-&pwr {
- pwr-regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
- };
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rng1 {
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index dcaab3e..a5cc01d 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -35,24 +35,7 @@
};
&adc {
- pinctrl-names = "default";
- pinctrl-0 = <&adc12_usb_pwr_pins_a>;
- vdd-supply = <&vdd>;
- vdda-supply = <&vdd>;
- vref-supply = <&vrefbuf>;
status = "okay";
- adc1: adc@0 {
- /*
- * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
- * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
- * 5 * (56 + 47kOhms) * 5pF => 2.5us.
- * Use arbitrary margin here (e.g. 5µs).
- */
- st,min-sample-time-nsecs = <5000>;
- /* ANA0, ANA1, USB Type-C CC1 & CC2 */
- st,adc-channels = <0 1 18 19>;
- status = "okay";
- };
};
&clk_hse {
@@ -127,7 +110,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4Q
+ CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
@@ -141,6 +124,8 @@
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
@@ -148,6 +133,8 @@
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
@@ -155,6 +142,8 @@
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
@@ -162,6 +151,8 @@
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts
index 4652253..624bf69 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dts
+++ b/arch/arm/dts/stm32mp157a-dk1.dts
@@ -25,6 +25,7 @@
};
memory@c0000000 {
+ device_type = "memory";
reg = <0xc0000000 0x20000000>;
};
@@ -92,11 +93,38 @@
"Playback" , "MCLK",
"Capture" , "MCLK",
"MICL" , "Mic Bias";
- dais = <&sai2a_port &sai2b_port>;
+ dais = <&sai2a_port &sai2b_port &i2s2_port>;
status = "okay";
};
};
+&adc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&adc12_ain_pins_a>, <&adc12_usb_cc_pins_a>;
+ vdd-supply = <&vdd>;
+ vdda-supply = <&vdd>;
+ vref-supply = <&vrefbuf>;
+ status = "disabled";
+ adc1: adc@0 {
+ /*
+ * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
+ * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
+ * 5 * (56 + 47kOhms) * 5pF => 2.5us.
+ * Use arbitrary margin here (e.g. 5us).
+ */
+ st,min-sample-time-nsecs = <5000>;
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 6 13 18 19>;
+ status = "okay";
+ };
+ adc2: adc@100 {
+ /* AIN connector, USB Type-C CC1 & CC2 */
+ st,adc-channels = <0 1 2 6 18 19>;
+ st,min-sample-time-nsecs = <5000>;
+ status = "okay";
+ };
+};
+
&cec {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cec_pins_b>;
@@ -146,9 +174,7 @@
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpiog>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <<dc_pins_a>;
- pinctrl-1 = <<dc_pins_sleep_a>;
+ #sound-dai-cells = <0>;
status = "okay";
ports {
@@ -161,6 +187,13 @@
remote-endpoint = <<dc_ep0_out>;
};
};
+
+ port@3 {
+ reg = <3>;
+ sii9022_tx_endpoint: endpoint {
+ remote-endpoint = <&i2s2_endpoint>;
+ };
+ };
};
};
@@ -244,7 +277,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
@@ -345,7 +378,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -364,6 +397,23 @@
};
};
+&i2s2 {
+ clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
+ clock-names = "pclk", "i2sclk", "x8k", "x11k";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2s2_pins_a>;
+ pinctrl-1 = <&i2s2_pins_sleep_a>;
+ status = "okay";
+
+ i2s2_port: port {
+ i2s2_endpoint: endpoint {
+ remote-endpoint = <&sii9022_tx_endpoint>;
+ format = "i2s";
+ mclk-fs = <256>;
+ };
+ };
+};
+
&ipcc {
status = "okay";
};
@@ -374,6 +424,9 @@
};
<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_pins_sleep_a>;
status = "okay";
port {
@@ -397,11 +450,9 @@
status = "okay";
};
-&pwr {
- pwr-regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
- };
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rng1 {
diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts
index 020ea0f..d26adcb 100644
--- a/arch/arm/dts/stm32mp157c-dk2.dts
+++ b/arch/arm/dts/stm32mp157c-dk2.dts
@@ -53,6 +53,19 @@
};
};
+&i2c1 {
+ touchscreen@38 {
+ compatible = "focaltech,ft6236";
+ reg = <0x38>;
+ interrupts = <2 2>;
+ interrupt-parent = <&gpiof>;
+ interrupt-controller;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ status = "okay";
+ };
+};
+
<dc {
status = "okay";
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
index b2ac494..347edf7 100644
--- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
@@ -107,7 +107,7 @@
CLK_UART6_HSI
CLK_UART78_HSI
CLK_SPDIF_PLL4P
- CLK_FDCAN_PLL4Q
+ CLK_FDCAN_PLL4R
CLK_SAI1_PLL3Q
CLK_SAI2_PLL3Q
CLK_SAI3_PLL3Q
@@ -121,6 +121,8 @@
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
@@ -128,6 +130,8 @@
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
@@ -135,6 +139,8 @@
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
@@ -142,6 +148,8 @@
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts
index bc4d7e1..ae4da39 100644
--- a/arch/arm/dts/stm32mp157c-ed1.dts
+++ b/arch/arm/dts/stm32mp157c-ed1.dts
@@ -84,10 +84,24 @@
gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
gpios-states = <0>;
- states = <1800000 0x1 2900000 0x0>;
+ states = <1800000 0x1>,
+ <2900000 0x0>;
};
};
+&dac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
+ vref-supply = <&vdda>;
+ status = "disabled";
+ dac1: dac@1 {
+ status = "okay";
+ };
+ dac2: dac@2 {
+ status = "okay";
+ };
+};
+
&dts {
status = "okay";
};
@@ -127,7 +141,7 @@
vddcore: buck1 {
regulator-name = "vddcore";
- regulator-min-microvolt = <800000>;
+ regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-initial-mode = <0>;
@@ -225,7 +239,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -263,11 +277,9 @@
status = "okay";
};
-&pwr {
- pwr-regulators {
- vdd-supply = <&vdd>;
- vdd_3v3_usbfs-supply = <&vdd_usb>;
- };
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
};
&rng1 {
diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts
index 89d29b5..bd8ffc1 100644
--- a/arch/arm/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/dts/stm32mp157c-ev1.dts
@@ -32,7 +32,6 @@
joystick {
compatible = "gpio-keys";
- #size-cells = <0>;
pinctrl-0 = <&joystick_pins>;
pinctrl-names = "default";
button-0 {
@@ -189,8 +188,8 @@
clocks = <&clk_ext_camera>;
clock-names = "xclk";
DOVDD-supply = <&v2v8>;
- powerdown-gpios = <&stmfx_pinctrl 18 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&stmfx_pinctrl 19 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
+ reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
rotation = <180>;
status = "okay";
@@ -223,7 +222,6 @@
joystick_pins: joystick {
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
- drive-push-pull;
bias-pull-down;
};
@@ -344,14 +342,12 @@
&usbh_ehci {
phys = <&usbphyc_port0>;
- phy-names = "usb";
status = "okay";
};
&usbotg_hs {
dr_mode = "peripheral";
phys = <&usbphyc_port1 0>;
- phy-names = "usb2-phy";
status = "okay";
};
diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 41aea75..22a9386 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -939,7 +939,7 @@
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
status = "disabled";
};
@@ -952,7 +952,7 @@
interrupt-names = "int0", "int1";
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
status = "disabled";
};
@@ -1110,36 +1110,26 @@
#reset-cells = <1>;
};
- pwr: pwr@50001000 {
- compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd";
- reg = <0x50001000 0x400>;
- system-power-controller;
- interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- st,sysrcc = <&rcc>;
- clocks = <&rcc PLL2_R>;
- clock-names = "phyclk";
+ pwr_regulators: pwr@50001000 {
+ compatible = "st,stm32mp1,pwr-reg";
+ reg = <0x50001000 0x10>;
- pwr-regulators {
- compatible = "st,stm32mp1,pwr-reg";
- st,tzcr = <&rcc 0x0 0x1>;
-
- reg11: reg11 {
- regulator-name = "reg11";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- };
+ reg11: reg11 {
+ regulator-name = "reg11";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ };
- reg18: reg18 {
- regulator-name = "reg18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
+ reg18: reg18 {
+ regulator-name = "reg18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
- usb33: usb33 {
- regulator-name = "usb33";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ usb33: usb33 {
+ regulator-name = "usb33";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
new file mode 100644
index 0000000..12f89b3
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp15xx-dhcom-u-boot.dtsi"
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
new file mode 100644
index 0000000..dd98c7a
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dts
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
+ */
+
+#include "stm32mp15xx-dhcom.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP15xx DHCOM Premium Developer Kit (2)";
+ compatible = "dh,stm32mp15xx-dhcom-pdk2", "st,stm32mp15x";
+
+ aliases {
+ serial0 = &uart4;
+ ethernet0 = ðernet0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ ethernet_vio: vioregulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vio";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpiog 3 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+ðernet0 {
+ status = "okay";
+ pinctrl-0 = <ðernet0_rmii_pins_a>;
+ pinctrl-1 = <ðernet0_rmii_pins_sleep_a>;
+ pinctrl-names = "default", "sleep";
+ phy-mode = "rmii";
+ max-speed = <100>;
+ phy-handle = <&phy0>;
+ st,eth_ref_clk_sel;
+ phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
+&pinctrl {
+ ethernet0_rmii_pins_a: rmii-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
+ bias-disable;
+ };
+ };
+
+ ethernet0_rmii_pins_sleep_a: rmii-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
+ <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
+ <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
+ <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
+ <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
+ <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
+ <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
+ };
+ };
+};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
new file mode 100644
index 0000000..6c952a5
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
+ */
+
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp157-u-boot.dtsi"
+#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
+
+/ {
+ aliases {
+ i2c1 = &i2c2;
+ i2c3 = &i2c4;
+ i2c4 = &i2c5;
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ spi0 = &qspi;
+ usb0 = &usbotg_hs;
+ };
+
+ config {
+ u-boot,boot-led = "heartbeat";
+ u-boot,error-led = "error";
+ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+ };
+
+ led {
+ red {
+ label = "error";
+ gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ status = "okay";
+ };
+
+ blue {
+ default-state = "on";
+ };
+ };
+};
+
+&i2c4 {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&pmic {
+ u-boot,dm-pre-reloc;
+};
+
+&flash0 {
+ u-boot,dm-spl;
+};
+
+&qspi {
+ u-boot,dm-spl;
+};
+
+&qspi_clk_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi_bk1_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&qspi_bk2_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&rcc {
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
+ cfg = < 2 80 0 0 0 PQR(1,0,0) >;
+ frac = < 0x800 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = < 2 65 1 0 0 PQR(1,1,1) >;
+ frac = < 0x1400 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+ pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = < 1 33 1 16 36 PQR(1,1,1) >;
+ frac = < 0x1a04 >;
+ u-boot,dm-pre-reloc;
+ };
+
+ /* VCO = 600.0 MHz => P = 50, Q = 50, R = 50 */
+ pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = < 1 49 11 11 11 PQR(1,1,1) >;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&sdmmc1 {
+ u-boot,dm-spl;
+};
+
+&sdmmc1_b4_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc1_dir_pins_a {
+ u-boot,dm-spl;
+ pins1 {
+ u-boot,dm-spl;
+ };
+ pins2 {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc2 {
+ u-boot,dm-spl;
+};
+
+&sdmmc2_b4_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&sdmmc2_d47_pins_a {
+ u-boot,dm-spl;
+ pins {
+ u-boot,dm-spl;
+ };
+};
+
+&uart4 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart4_pins_a {
+ u-boot,dm-pre-reloc;
+ pins1 {
+ u-boot,dm-pre-reloc;
+ };
+ pins2 {
+ u-boot,dm-pre-reloc;
+ /* pull-up on rx to avoid floating level */
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm/dts/stm32mp15xx-dhcom.dtsi b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
new file mode 100644
index 0000000..bed69c9
--- /dev/null
+++ b/arch/arm/dts/stm32mp15xx-dhcom.dtsi
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019 Marek Vasut <marex@denx.de>
+ */
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157xaa-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/st,stpmic1.h>
+
+/ {
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xC0000000 0x40000000>;
+ };
+};
+
+&cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cec_pins_a>;
+ status = "okay";
+};
+
+&dcmi {
+ status = "okay";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dcmi_pins_a>;
+ pinctrl-1 = <&dcmi_sleep_pins_a>;
+};
+
+&dts {
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&v3v3>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo5-supply = <&v3v3>;
+ ldo6-supply = <&v3v3>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ vdda: ldo1 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO1 0>;
+ };
+
+ v2v8: ldo2 {
+ regulator-name = "v2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ interrupts = <IT_CURLIM_LDO2 0>;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ interrupts = <IT_CURLIM_LDO4 0>;
+ };
+
+ vdd_sd: ldo5 {
+ regulator-name = "vdd_sd";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ interrupts = <IT_CURLIM_LDO5 0>;
+ regulator-boot-on;
+ };
+
+ v1v8: ldo6 {
+ regulator-name = "v1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ interrupts = <IT_CURLIM_LDO6 0>;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ interrupts = <IT_OCP_BOOST 0>;
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ interrupts = <IT_OCP_OTG 0>;
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ interrupts = <IT_OCP_SWOUT 0>;
+ regulator-active-discharge;
+ };
+ };
+
+ onkey {
+ compatible = "st,stpmic1-onkey";
+ interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
+ interrupt-names = "onkey-falling", "onkey-rising";
+ power-off-time-sec = <10>;
+ status = "okay";
+ };
+
+ watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+};
+
+&ipcc {
+ status = "okay";
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&m4_rproc {
+ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
+ mbox-names = "vq0", "vq1", "shutdown";
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&qspi {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
+ pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>;
+ reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash0: mx66l51235l@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ flash1: mx66l51235l@1 {
+ compatible = "jedec,spi-nor";
+ reg = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
+ broken-cd;
+ st,sig-dir;
+ st,neg-edge;
+ st,use-ckin;
+ bus-width = <4>;
+ vmmc-supply = <&vdd_sd>;
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,sig-dir;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>;
+ status = "disabled";
+};
+
+&timers2 {
+ /* spare dmas for other usage (un-delete to enable pwm capture) */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ timer@1 {
+ status = "okay";
+ };
+};
+
+&timers6 {
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ timer@5 {
+ status = "okay";
+ };
+};
+
+&timers8 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm8_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ timer@7 {
+ status = "okay";
+ };
+};
+
+&timers12 {
+ /delete-property/dmas;
+ /delete-property/dma-names;
+ status = "disabled";
+ pwm {
+ pinctrl-0 = <&pwm12_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ timer@11 {
+ status = "okay";
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+&usbh_ehci {
+ phys = <&usbphyc_port0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&usbotg_hs {
+ dr_mode = "peripheral";
+ phys = <&usbphyc_port1 0>;
+ phy-names = "usb2-phy";
+ vbus-supply = <&vbus_otg>;
+ status = "okay";
+};
+
+&usbphyc {
+ status = "okay";
+};
+
+&usbphyc_port0 {
+ phy-supply = <&vdd_usb>;
+};
+
+&usbphyc_port1 {
+ phy-supply = <&vdd_usb>;
+};
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 137178a..e4d621d 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -73,6 +73,14 @@
Evalulation board (EV1) or Discovery board (DK1 and DK2).
The difference between board are managed with devicetree
+config TARGET_DH_STM32MP1_PDK2
+ bool "DH STM32MP1 PDK2"
+ select STM32MP15x
+ imply BOOTCOUNT_LIMIT
+ imply CMD_BOOTCOUNT
+ help
+ Target the DH PDK2 development kit with STM32MP15x SoM.
+
endchoice
config STM32MP1_TRUSTED
@@ -158,5 +166,6 @@
endif
source "board/st/stm32mp1/Kconfig"
+source "board/dhelectronics/dh_stm32mp1/Kconfig"
endif
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index de7891b..ea0bd94 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -342,6 +342,9 @@
case CPU_REVB:
cpu_r = "B";
break;
+ case CPU_REVZ:
+ cpu_r = "Z";
+ break;
default:
cpu_r = "?";
break;
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h
index 88126b8..f063600 100644
--- a/arch/arm/mach-stm32mp/include/mach/stm32.h
+++ b/arch/arm/mach-stm32mp/include/mach/stm32.h
@@ -37,7 +37,6 @@
/* enumerated used to identify the SYSCON driver instance */
enum {
STM32MP_SYSCON_UNKNOWN,
- STM32MP_SYSCON_PWR,
STM32MP_SYSCON_SYSCFG,
};
diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
index 47e5792..da46c11 100644
--- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h
+++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h
@@ -16,6 +16,7 @@
#define CPU_REVA 0x1000
#define CPU_REVB 0x2000
+#define CPU_REVZ 0x2001
/* return CPU_REV constants */
u32 get_cpu_rev(void);
diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c
index 4559ef5..b52e1e8 100644
--- a/arch/arm/mach-stm32mp/pwr_regulator.c
+++ b/arch/arm/mach-stm32mp/pwr_regulator.c
@@ -6,8 +6,8 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <regmap.h>
#include <syscon.h>
+#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#include <power/pmic.h>
@@ -28,7 +28,7 @@
};
struct stm32mp_pwr_priv {
- struct regmap *regmap;
+ fdt_addr_t base;
};
static int stm32mp_pwr_write(struct udevice *dev, uint reg,
@@ -40,7 +40,9 @@
if (len != 4)
return -EINVAL;
- return regmap_write(priv->regmap, STM32MP_PWR_CR3, val);
+ writel(val, priv->base + STM32MP_PWR_CR3);
+
+ return 0;
}
static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
@@ -51,21 +53,18 @@
if (len != 4)
return -EINVAL;
- return regmap_read(priv->regmap, STM32MP_PWR_CR3, (u32 *)buff);
+ *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3);
+
+ return 0;
}
static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
{
struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
- struct regmap *regmap;
- regmap = syscon_get_regmap_by_driver_data(STM32MP_SYSCON_PWR);
- if (IS_ERR(regmap)) {
- pr_err("%s: unable to find regmap (%ld)\n", __func__,
- PTR_ERR(regmap));
- return PTR_ERR(regmap);
- }
- priv->regmap = regmap;
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
return 0;
}
diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c
index 6070837..3e61ce4 100644
--- a/arch/arm/mach-stm32mp/syscon.c
+++ b/arch/arm/mach-stm32mp/syscon.c
@@ -9,7 +9,6 @@
#include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = {
- { .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR },
{ .compatible = "st,stm32mp157-syscfg",
.data = STM32MP_SYSCON_SYSCFG },
{ }
diff --git a/board/dhelectronics/dh_stm32mp1/Kconfig b/board/dhelectronics/dh_stm32mp1/Kconfig
new file mode 100644
index 0000000..8eab986
--- /dev/null
+++ b/board/dhelectronics/dh_stm32mp1/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_DH_STM32MP1_PDK2
+
+config SYS_BOARD
+ default "dh_stm32mp1"
+
+config SYS_VENDOR
+ default "dhelectronics"
+
+config SYS_CONFIG_NAME
+ default "stm32mp1"
+
+config ENV_SECT_SIZE
+ default 0x10000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET
+ default 0x1E0000 if ENV_IS_IN_SPI_FLASH
+
+config ENV_OFFSET_REDUND
+ default 0x1F0000 if ENV_IS_IN_SPI_FLASH
+
+endif
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
new file mode 100644
index 0000000..1511ecb
--- /dev/null
+++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
@@ -0,0 +1,7 @@
+DH_STM32MP1_PDK2 BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: arch/arm/dts/stm32mp15xx-dhcom*
+F: board/dhelectronics/dh_stm32mp1/
+F: configs/stm32mp15_dhcom_basic_defconfig
+F: include/configs/stm32mp1.h
diff --git a/board/dhelectronics/dh_stm32mp1/Makefile b/board/dhelectronics/dh_stm32mp1/Makefile
new file mode 100644
index 0000000..b42c4e4
--- /dev/null
+++ b/board/dhelectronics/dh_stm32mp1/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+#
+# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += ../../st/stm32mp1/spl.o
+endif
+
+obj-y += ../../st/stm32mp1/board.o board.o
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
new file mode 100644
index 0000000..b663696
--- /dev/null
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -0,0 +1,689 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#include <common.h>
+#include <adc.h>
+#include <asm/arch/stm32.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <bootm.h>
+#include <clk.h>
+#include <config.h>
+#include <dm.h>
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <g_dnl.h>
+#include <generic-phy.h>
+#include <hang.h>
+#include <i2c.h>
+#include <i2c_eeprom.h>
+#include <init.h>
+#include <led.h>
+#include <memalign.h>
+#include <misc.h>
+#include <mtd.h>
+#include <mtd_node.h>
+#include <netdev.h>
+#include <phy.h>
+#include <power/regulator.h>
+#include <remoteproc.h>
+#include <reset.h>
+#include <syscon.h>
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <watchdog.h>
+
+/* SYSCFG registers */
+#define SYSCFG_BOOTR 0x00
+#define SYSCFG_PMCSETR 0x04
+#define SYSCFG_IOCTRLSETR 0x18
+#define SYSCFG_ICNR 0x1C
+#define SYSCFG_CMPCR 0x20
+#define SYSCFG_CMPENSETR 0x24
+#define SYSCFG_PMCCLRR 0x44
+
+#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
+#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
+
+#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
+#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
+#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
+#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
+
+#define SYSCFG_CMPCR_SW_CTRL BIT(1)
+#define SYSCFG_CMPCR_READY BIT(8)
+
+#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
+
+#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
+#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
+
+#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
+
+#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
+#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
+#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
+#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
+
+/*
+ * Get a global data pointer
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+int setup_mac_address(void)
+{
+ struct udevice *dev;
+ ofnode eeprom;
+ unsigned char enetaddr[6];
+ int ret;
+
+ ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+ if (ret) /* ethaddr is already set */
+ return 0;
+
+ eeprom = ofnode_path("/soc/i2c@5c002000/eeprom@50");
+ if (!ofnode_valid(eeprom)) {
+ printf("Invalid hardware path to EEPROM!\n");
+ return -ENODEV;
+ }
+
+ ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
+ if (ret) {
+ printf("Cannot find EEPROM!\n");
+ return ret;
+ }
+
+ ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
+ if (ret) {
+ printf("Error reading configuration EEPROM!\n");
+ return ret;
+ }
+
+ if (is_valid_ethaddr(enetaddr))
+ eth_env_set_enetaddr("ethaddr", enetaddr);
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ char *mode;
+ const char *fdt_compat;
+ int fdt_compat_len;
+
+ if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
+ mode = "trusted with OP-TEE";
+ else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
+ mode = "trusted";
+ else
+ mode = "basic";
+
+ printf("Board: stm32mp1 in %s mode", mode);
+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+ &fdt_compat_len);
+ if (fdt_compat && fdt_compat_len)
+ printf(" (%s)", fdt_compat);
+ puts("\n");
+
+ return 0;
+}
+
+static void board_key_check(void)
+{
+#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
+ ofnode node;
+ struct gpio_desc gpio;
+ enum forced_boot_mode boot_mode = BOOT_NORMAL;
+
+ node = ofnode_path("/config");
+ if (!ofnode_valid(node)) {
+ debug("%s: no /config node?\n", __func__);
+ return;
+ }
+#ifdef CONFIG_FASTBOOT
+ if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
+ &gpio, GPIOD_IS_IN)) {
+ debug("%s: could not find a /config/st,fastboot-gpios\n",
+ __func__);
+ } else {
+ if (dm_gpio_get_value(&gpio)) {
+ puts("Fastboot key pressed, ");
+ boot_mode = BOOT_FASTBOOT;
+ }
+
+ dm_gpio_free(NULL, &gpio);
+ }
+#endif
+#ifdef CONFIG_CMD_STM32PROG
+ if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
+ &gpio, GPIOD_IS_IN)) {
+ debug("%s: could not find a /config/st,stm32prog-gpios\n",
+ __func__);
+ } else {
+ if (dm_gpio_get_value(&gpio)) {
+ puts("STM32Programmer key pressed, ");
+ boot_mode = BOOT_STM32PROG;
+ }
+ dm_gpio_free(NULL, &gpio);
+ }
+#endif
+
+ if (boot_mode != BOOT_NORMAL) {
+ puts("entering download mode...\n");
+ clrsetbits_le32(TAMP_BOOT_CONTEXT,
+ TAMP_BOOT_FORCED_MASK,
+ boot_mode);
+ }
+#endif
+}
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+
+#include <usb/dwc2_udc.h>
+int g_dnl_board_usb_cable_connected(void)
+{
+ struct udevice *dwc2_udc_otg;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
+ DM_GET_DRIVER(dwc2_udc_otg),
+ &dwc2_udc_otg);
+ if (!ret)
+ debug("dwc2_udc_otg init failed\n");
+
+ return dwc2_udc_B_session_valid(dwc2_udc_otg);
+}
+
+#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
+#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ if (!strcmp(name, "usb_dnl_dfu"))
+ put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
+ else if (!strcmp(name, "usb_dnl_fastboot"))
+ put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
+ &dev->idProduct);
+ else
+ put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
+
+ return 0;
+}
+
+#endif /* CONFIG_USB_GADGET */
+
+#ifdef CONFIG_LED
+static int get_led(struct udevice **dev, char *led_string)
+{
+ char *led_name;
+ int ret;
+
+ led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
+ if (!led_name) {
+ pr_debug("%s: could not find %s config string\n",
+ __func__, led_string);
+ return -ENOENT;
+ }
+ ret = led_get_by_label(led_name, dev);
+ if (ret) {
+ debug("%s: get=%d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int setup_led(enum led_state_t cmd)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = get_led(&dev, "u-boot,boot-led");
+ if (ret)
+ return ret;
+
+ ret = led_set_state(dev, cmd);
+ return ret;
+}
+#endif
+
+static void __maybe_unused led_error_blink(u32 nb_blink)
+{
+#ifdef CONFIG_LED
+ int ret;
+ struct udevice *led;
+ u32 i;
+#endif
+
+ if (!nb_blink)
+ return;
+
+#ifdef CONFIG_LED
+ ret = get_led(&led, "u-boot,error-led");
+ if (!ret) {
+ /* make u-boot,error-led blinking */
+ /* if U32_MAX and 125ms interval, for 17.02 years */
+ for (i = 0; i < 2 * nb_blink; i++) {
+ led_set_state(led, LEDST_TOGGLE);
+ mdelay(125);
+ WATCHDOG_RESET();
+ }
+ }
+#endif
+
+ /* infinite: the boot process must be stopped */
+ if (nb_blink == U32_MAX)
+ hang();
+}
+
+static void sysconf_init(void)
+{
+#ifndef CONFIG_STM32MP1_TRUSTED
+ u8 *syscfg;
+#ifdef CONFIG_DM_REGULATOR
+ struct udevice *pwr_dev;
+ struct udevice *pwr_reg;
+ struct udevice *dev;
+ int ret;
+ u32 otp = 0;
+#endif
+ u32 bootr;
+
+ syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ /* interconnect update : select master using the port 1 */
+ /* LTDC = AXI_M9 */
+ /* GPU = AXI_M8 */
+ /* today information is hardcoded in U-Boot */
+ writel(BIT(9), syscfg + SYSCFG_ICNR);
+
+ /* disable Pull-Down for boot pin connected to VDD */
+ bootr = readl(syscfg + SYSCFG_BOOTR);
+ bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
+ bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
+ writel(bootr, syscfg + SYSCFG_BOOTR);
+
+#ifdef CONFIG_DM_REGULATOR
+ /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
+ * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
+ * The customer will have to disable this for low frequencies
+ * or if AFMUX is selected but the function not used, typically for
+ * TRACE. Otherwise, impact on power consumption.
+ *
+ * WARNING:
+ * enabling High Speed mode while VDD>2.7V
+ * with the OTP product_below_2v5 (OTP 18, BIT 13)
+ * erroneously set to 1 can damage the IC!
+ * => U-Boot set the register only if VDD < 2.7V (in DT)
+ * but this value need to be consistent with board design
+ */
+ ret = uclass_get_device_by_driver(UCLASS_PMIC,
+ DM_GET_DRIVER(stm32mp_pwr_pmic),
+ &pwr_dev);
+ if (!ret) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(stm32mp_bsec),
+ &dev);
+ if (ret) {
+ pr_err("Can't find stm32mp_bsec driver\n");
+ return;
+ }
+
+ ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
+ if (ret > 0)
+ otp = otp & BIT(13);
+
+ /* get VDD = vdd-supply */
+ ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
+ &pwr_reg);
+
+ /* check if VDD is Low Voltage */
+ if (!ret) {
+ if (regulator_get_value(pwr_reg) < 2700000) {
+ writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
+ SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
+ SYSCFG_IOCTRLSETR_HSLVEN_ETH |
+ SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
+ SYSCFG_IOCTRLSETR_HSLVEN_SPI,
+ syscfg + SYSCFG_IOCTRLSETR);
+
+ if (!otp)
+ pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
+ } else {
+ if (otp)
+ pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
+ }
+ } else {
+ debug("VDD unknown");
+ }
+ }
+#endif
+
+ /* activate automatic I/O compensation
+ * warning: need to ensure CSI enabled and ready in clock driver
+ */
+ writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
+
+ while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
+ ;
+ clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
+#endif
+}
+
+/* board dependent setup after realloc */
+int board_init(void)
+{
+ struct udevice *dev;
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
+
+ /* probe all PINCTRL for hog */
+ for (uclass_first_device(UCLASS_PINCTRL, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ pr_debug("probe pincontrol = %s\n", dev->name);
+ }
+
+ board_key_check();
+
+#ifdef CONFIG_DM_REGULATOR
+ regulators_enable_boot_on(_DEBUG);
+#endif
+
+ sysconf_init();
+
+ if (CONFIG_IS_ENABLED(CONFIG_LED))
+ led_default_state();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ char *boot_device;
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ const void *fdt_compat;
+ int fdt_compat_len;
+
+ fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
+ &fdt_compat_len);
+ if (fdt_compat && fdt_compat_len) {
+ if (strncmp(fdt_compat, "st,", 3) != 0)
+ env_set("board_name", fdt_compat);
+ else
+ env_set("board_name", fdt_compat + 3);
+ }
+#endif
+
+ /* Check the boot-source to disable bootdelay */
+ boot_device = env_get("boot_device");
+ if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
+ env_set("bootdelay", "0");
+
+ return 0;
+}
+
+void board_quiesce_devices(void)
+{
+#ifdef CONFIG_LED
+ setup_led(LEDST_OFF);
+#endif
+}
+
+/* eth init function : weak called in eqos driver */
+int board_interface_eth_init(struct udevice *dev,
+ phy_interface_t interface_type)
+{
+ u8 *syscfg;
+ u32 value;
+ bool eth_clk_sel_reg = false;
+ bool eth_ref_clk_sel_reg = false;
+
+ /* Gigabit Ethernet 125MHz clock selection. */
+ eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
+
+ /* Ethernet 50Mhz RMII clock selection */
+ eth_ref_clk_sel_reg =
+ dev_read_bool(dev, "st,eth_ref_clk_sel");
+
+ syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
+
+ if (!syscfg)
+ return -ENODEV;
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
+ SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+ debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
+ break;
+ case PHY_INTERFACE_MODE_GMII:
+ if (eth_clk_sel_reg)
+ value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
+ SYSCFG_PMCSETR_ETH_CLK_SEL;
+ else
+ value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
+ debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if (eth_ref_clk_sel_reg)
+ value = SYSCFG_PMCSETR_ETH_SEL_RMII |
+ SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
+ else
+ value = SYSCFG_PMCSETR_ETH_SEL_RMII;
+ debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ if (eth_clk_sel_reg)
+ value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
+ SYSCFG_PMCSETR_ETH_CLK_SEL;
+ else
+ value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
+ debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
+ break;
+ default:
+ debug("%s: Do not manage %d interface\n",
+ __func__, interface_type);
+ /* Do not manage others interfaces */
+ return -EINVAL;
+ }
+
+ /* clear and set ETH configuration bits */
+ writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
+ SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
+ syscfg + SYSCFG_PMCCLRR);
+ writel(value, syscfg + SYSCFG_PMCSETR);
+
+ return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ if (prio)
+ return ENVL_UNKNOWN;
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+ return ENVL_SPI_FLASH;
+#else
+ return ENVL_NOWHERE;
+#endif
+}
+
+#ifdef CONFIG_SYS_MTDPARTS_RUNTIME
+
+#define MTDPARTS_LEN 256
+#define MTDIDS_LEN 128
+
+/**
+ * The mtdparts_nand0 and mtdparts_nor0 variable tends to be long.
+ * If we need to access it before the env is relocated, then we need
+ * to use our own stack buffer. gd->env_buf will be too small.
+ *
+ * @param buf temporary buffer pointer MTDPARTS_LEN long
+ * @return mtdparts variable string, NULL if not found
+ */
+static const char *env_get_mtdparts(const char *str, char *buf)
+{
+ if (gd->flags & GD_FLG_ENV_READY)
+ return env_get(str);
+ if (env_get_f(str, buf, MTDPARTS_LEN) != -1)
+ return buf;
+
+ return NULL;
+}
+
+/**
+ * update the variables "mtdids" and "mtdparts" with content of mtdparts_<dev>
+ */
+static void board_get_mtdparts(const char *dev,
+ char *mtdids,
+ char *mtdparts)
+{
+ char env_name[32] = "mtdparts_";
+ char tmp_mtdparts[MTDPARTS_LEN];
+ const char *tmp;
+
+ /* name of env variable to read = mtdparts_<dev> */
+ strcat(env_name, dev);
+ tmp = env_get_mtdparts(env_name, tmp_mtdparts);
+ if (tmp) {
+ /* mtdids: "<dev>=<dev>, ...." */
+ if (mtdids[0] != '\0')
+ strcat(mtdids, ",");
+ strcat(mtdids, dev);
+ strcat(mtdids, "=");
+ strcat(mtdids, dev);
+
+ /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */
+ if (mtdparts[0] != '\0')
+ strncat(mtdparts, ";", MTDPARTS_LEN);
+ else
+ strcat(mtdparts, "mtdparts=");
+ strncat(mtdparts, dev, MTDPARTS_LEN);
+ strncat(mtdparts, ":", MTDPARTS_LEN);
+ strncat(mtdparts, tmp, MTDPARTS_LEN);
+ }
+}
+
+void board_mtdparts_default(const char **mtdids, const char **mtdparts)
+{
+ struct udevice *dev;
+ static char parts[3 * MTDPARTS_LEN + 1];
+ static char ids[MTDIDS_LEN + 1];
+ static bool mtd_initialized;
+
+ if (mtd_initialized) {
+ *mtdids = ids;
+ *mtdparts = parts;
+ return;
+ }
+
+ memset(parts, 0, sizeof(parts));
+ memset(ids, 0, sizeof(ids));
+
+ /* probe all MTD devices */
+ for (uclass_first_device(UCLASS_MTD, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ pr_debug("mtd device = %s\n", dev->name);
+ }
+
+ if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
+ board_get_mtdparts("nor0", ids, parts);
+
+ mtd_initialized = true;
+ *mtdids = ids;
+ *mtdparts = parts;
+ debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SET_DFU_ALT_INFO
+#define DFU_ALT_BUF_LEN SZ_1K
+
+static void board_get_alt_info(const char *dev, char *buff)
+{
+ char var_name[32] = "dfu_alt_info_";
+ int ret;
+
+ ALLOC_CACHE_ALIGN_BUFFER(char, tmp_alt, DFU_ALT_BUF_LEN);
+
+ /* name of env variable to read = dfu_alt_info_<dev> */
+ strcat(var_name, dev);
+ ret = env_get_f(var_name, tmp_alt, DFU_ALT_BUF_LEN);
+ if (ret) {
+ if (buff[0] != '\0')
+ strcat(buff, "&");
+ strncat(buff, tmp_alt, DFU_ALT_BUF_LEN);
+ }
+}
+
+void set_dfu_alt_info(char *interface, char *devstr)
+{
+ struct udevice *dev;
+
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
+
+ if (env_get("dfu_alt_info"))
+ return;
+
+ memset(buf, 0, sizeof(buf));
+
+ /* probe all MTD devices */
+ mtd_probe_devices();
+
+ board_get_alt_info("ram", buf);
+
+ if (!uclass_get_device(UCLASS_MMC, 0, &dev))
+ board_get_alt_info("mmc0", buf);
+
+ if (!uclass_get_device(UCLASS_MMC, 1, &dev))
+ board_get_alt_info("mmc1", buf);
+
+ if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev))
+ board_get_alt_info("nor0", buf);
+
+ env_set("dfu_alt_info", buf);
+ puts("DFU alt info setting: done\n");
+}
+#endif
+
+static void board_copro_image_process(ulong fw_image, size_t fw_size)
+{
+ int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
+
+ if (!rproc_is_initialized())
+ if (rproc_init()) {
+ printf("Remote Processor %d initialization failed\n",
+ id);
+ return;
+ }
+
+ ret = rproc_load(id, fw_image, fw_size);
+ printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
+ id, fw_image, fw_size, ret ? " Failed!" : " Success!");
+
+ if (!ret) {
+ rproc_start(id);
+ env_set("copro_state", "booted");
+ }
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README
index f2069bc..5d7465a 100644
--- a/board/st/stm32mp1/README
+++ b/board/st/stm32mp1/README
@@ -3,8 +3,8 @@
# Copyright (C) 2018 STMicroelectronics - All Rights Reserved
#
-U-Boot on STMicroelectronics STM32MP1
-======================================
+U-Boot on STMicroelectronics STM32MP15x
+=======================================
1. Summary
==========
@@ -12,12 +12,12 @@
2. Supported devices
====================
-U-Boot supports one STMP32MP1 SoCs: STM32MP157
+U-Boot supports STMP32MP15x SoCs: STM32MP157, STM32MP153 and STM32MP151
-The STM32MP157 is a Cortex-A MPU aimed at various applications.
+The STM32MP15x is a Cortex-A MPU aimed at various applications.
It features:
-- Dual core Cortex-A7 application core
-- 2D/3D image composition with GPU
+- Dual core Cortex-A7 application core (Single on STM32MP151)
+- 2D/3D image composition with GPU (only on STM32MP157)
- Standard memories interface support
- Standard connectivity, widely inherited from the STM32 MCU family
- Comprehensive security support
@@ -37,11 +37,11 @@
4. Fuse
Currently the following boards are supported:
-+ stm32mp157c-ev1
-+ stm32mp157c-ed1
-+ stm32mp157a-dk1
-+ stm32mp157c-dk2
-+ stm32mp157a-avenger96
++ stm32mp157a-avenger96.dts
++ stm32mp157a-dk1.dts
++ stm32mp157c-dk2.dts
++ stm32mp157c-ed1.dts
++ stm32mp157c-ev1.dts
3. Boot Sequences
=================
@@ -74,7 +74,7 @@
U-Boot is running in secure mode and provide a secure monitor to the kernel
with only PSCI support (Power State Coordination Interface defined by ARM).
-All the STM32MP1 boards supported by U-Boot use the same generic board
+All the STM32MP15x boards supported by U-Boot use the same generic board
stm32mp1 which support all the bootable devices.
Each board is configurated only with the associated device tree.
@@ -108,7 +108,7 @@
+ install package needed in U-Boot makefile
(libssl-dev, swig, libpython-dev...)
+ install ARMv7 toolchain for 32bit Cortex-A (from Linaro,
- from SDK for STM32MP1, or any crosstoolchains from your distribution)
+ from SDK for STM32MP15x, or any crosstoolchains from your distribution)
2. Set the cross compiler:
@@ -323,8 +323,7 @@
# ext4load mmc 0:4 0xC0000000 u-boot.img
# mmc dev 1
# part start mmc 1 1 partstart
- # part size mmc 1 1 partsize
- # mmc write ${fileaddr} ${partstart} ${partsize}
+ # mmc write ${fileaddr} ${partstart} ${filesize}
To boot from eMMC, select BootPinMode = 0 1 0 and reset.
@@ -334,14 +333,27 @@
Please read doc/README.enetaddr for the implementation guidelines for mac id
usage. Basically, environment has precedence over board specific storage.
-Mac id storage and retrieval in stm32mp otp :
+For STMicroelectonics board, it is retrieved in STM32MP15x otp :
- OTP_57[31:0] = MAC_ADDR[31:0]
- OTP_58[15:0] = MAC_ADDR[47:32]
To program a MAC address on virgin OTP words above, you can use the fuse command
on bank 0 to access to internal OTP:
- example to set mac address "12:34:56:78:9a:bc"
+ Prerequisite: check if a MAC address isn't yet programmed in OTP
+
+ 1- check OTP: their value must be equal to 0
+
+ STM32MP> fuse sense 0 57 2
+ Sensing bank 0:
+ Word 0x00000039: 00000000 00000000
+
+ 2- check environment variable
+
+ STM32MP> env print ethaddr
+ ## Error: "ethaddr" not defined
+
+ Example to set mac address "12:34:56:78:9a:bc"
1- Write OTP
STM32MP> fuse prog -y 0 57 0x78563412 0x0000bc9a
@@ -355,9 +367,13 @@
### Setting environment from OTP MAC address = "12:34:56:78:9a:bc"
4 check env update
- STM32MP> print ethaddr
+ STM32MP> env print ethaddr
ethaddr=12:34:56:78:9a:bc
+warning:: This MAC address provisioning can't be executed twice on the same
+ board as the OTP are protected. It is already done for the board
+ provided by STMicroelectronics.
+
10. Coprocessor firmware
========================
diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
index ca76579..c36e765 100644
--- a/board/st/stm32mp1/stm32mp1.c
+++ b/board/st/stm32mp1/stm32mp1.c
@@ -7,6 +7,7 @@
#include <bootm.h>
#include <clk.h>
#include <config.h>
+#include <dfu.h>
#include <dm.h>
#include <env.h>
#include <env_internal.h>
@@ -1011,7 +1012,7 @@
#include <dfu.h>
#include <power/stpmic1.h>
-int dfu_otp_read(u64 offset, u8 *buffer, long *size)
+static int dfu_otp_read(u64 offset, u8 *buffer, long *size)
{
struct udevice *dev;
int ret;
@@ -1031,7 +1032,7 @@
return 0;
}
-int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
+static int dfu_pmic_read(u64 offset, u8 *buffer, long *size)
{
int ret;
#ifdef CONFIG_PMIC_STPMIC1
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
new file mode 100644
index 0000000..921dea2
--- /dev/null
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -0,0 +1,138 @@
+CONFIG_ARM=y
+CONFIG_ARCH_STM32MP=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_TARGET_DH_STM32MP1_PDK2=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_SPL_TEXT_BASE=0x2FFC2500
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SYS_PROMPT="STM32MP> "
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="stm32mp15xx-dhcom-pdk2"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=10000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_IP_DEFRAG=y
+CONFIG_TFTP_BLOCKSIZE=1536
+CONFIG_STM32_ADC=y
+CONFIG_SPL_BLOCK_CACHE=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_VIRT=y
+CONFIG_DM_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_STM32=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_STM32F7=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_STM32_IPCC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_STM32_SDMMC2=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_PHY=y
+CONFIG_PHY_STM32_USBPHYC=y
+CONFIG_PINCONF=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_PINCTRL_STMFX=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_STPMIC1=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_REGULATOR_STM32_VREFBUF=y
+CONFIG_DM_REGULATOR_STPMIC1=y
+CONFIG_REMOTEPROC_STM32_COPRO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_STM32=y
+CONFIG_SERIAL_RX_BUFFER=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_STM32_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="dh"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0483
+CONFIG_USB_GADGET_PRODUCT_NUM=0x5720
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=1280
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_LZO=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index ec1d703..a3d4279 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -12,6 +12,9 @@
in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
file.
+This parent node may optionally have additional children nodes which define
+specific init values for RCC elements.
+
The added properties for clock tree initialization are:
Required properties:
@@ -78,13 +81,16 @@
>;
Optional Properties:
-- st,pll : A specific PLL configuration, including frequency.
+- children for a PLL configuration with "st,stm32mp1-pll" compatible
- PLL children nodes for PLL1 to PLL4 (see ref manual for details)
- are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
- PLLx is off when the associated node is absent.
+ each PLL children nodes for PLL1 to PLL4 (see ref manual for details)
+ are listed with associated reg 0 to 3.
+ PLLx is off when the associated node is absent or deactivated.
Here are the available properties for each PLL node:
+ - compatible: should be "st,stm32mp1-pll"
+
+ - reg: index of the pll instance
- cfg: The parameters for PLL configuration in the following order:
DIVM DIVN DIVP DIVQ DIVR Output.
@@ -118,18 +124,26 @@
Example:
st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
cfg = < 1 53 0 0 0 1 >;
frac = < 0x810 >;
};
st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
cfg = < 1 43 1 0 0 PQR(0,1,1) >;
csg = < 10 20 1 >;
};
st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
cfg = < 2 85 3 13 3 0 >;
csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
};
st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
cfg = < 2 78 4 7 9 3 >;
};
@@ -277,6 +291,8 @@
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
@@ -347,6 +363,8 @@
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
@@ -355,6 +373,8 @@
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
R = 533 (DDR) */
pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
@@ -362,6 +382,8 @@
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
frac = < 0x1a04 >;
u-boot,dm-pre-reloc;
@@ -369,6 +391,8 @@
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
diff --git a/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt b/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
index 70e76be..ad2bef8 100644
--- a/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
+++ b/doc/device-tree-bindings/mtd/stm32-fmc2-nand.txt
@@ -18,8 +18,10 @@
- dmas: DMA specifiers (see: dma/stm32-mdma.txt)
- dma-names: Must be "tx", "rx" and "ecc"
-Optional children nodes:
-Children nodes represent the available NAND chips.
+* NAND device bindings:
+
+Required properties:
+- reg: describes the CS lines assigned to the NAND device.
Optional properties:
- nand-on-flash-bbt: see nand.txt
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index da66bde..fd8c821 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -1218,7 +1218,7 @@
}
static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
- int lsedrv)
+ u32 lsedrv)
{
u32 value;
@@ -1651,8 +1651,8 @@
unsigned int clkdiv[CLKDIV_NB];
unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
ofnode plloff[_PLL_NB];
- int ret;
- int i, len;
+ int ret, len;
+ uint i;
int lse_css = 0;
const u32 *pkcs_cell;
@@ -1698,7 +1698,8 @@
stm32mp1_lsi_set(rcc, 1);
if (priv->osc[_LSE]) {
- int bypass, digbyp, lsedrv;
+ int bypass, digbyp;
+ u32 lsedrv;
struct udevice *dev = priv->osc_dev[_LSE];
bypass = dev_read_bool(dev, "st,bypass");
diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c
index c8e61e2..b0e43ae 100644
--- a/drivers/pinctrl/pinctrl-stmfx.c
+++ b/drivers/pinctrl/pinctrl-stmfx.c
@@ -352,11 +352,12 @@
int ret;
struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
- id = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
- if (id < 0) {
- dev_err(dev, "error reading chip id: %d\n", id);
+ ret = dm_i2c_reg_read(dev, STMFX_REG_CHIP_ID);
+ if (ret < 0) {
+ dev_err(dev, "error reading chip id: %d\n", ret);
return ret;
}
+ id = (u8)ret;
/*
* Check that ID is the complement of the I2C address:
* STMFX I2C address follows the 7-bit format (MSB), that's why
diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h
index a8a58f3..f393aa0 100644
--- a/include/configs/stih410-b2260.h
+++ b/include/configs/stih410-b2260.h
@@ -19,6 +19,12 @@
/* Environment */
+/*
+ * For booting Linux, use the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_BOOTM_LEN SZ_16M
@@ -34,8 +40,6 @@
"fdt_addr_r=0x47000000\0" \
"scriptaddr=0x50000000\0" \
"pxefile_addr_r=0x50100000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
"ramdisk_addr_r=0x48000000\0" \
BOOTENV
diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h
index 7a17222..a715031 100644
--- a/include/configs/stm32f429-evaluation.h
+++ b/include/configs/stm32f429-evaluation.h
@@ -7,6 +7,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
+
+/* For booting Linux, use the first 16MB of memory */
+#define CONFIG_SYS_BOOTMAPSZ SZ_16M
+
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
@@ -40,12 +45,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x00008000\0" \
"fdtfile=stm32429i-eval.dtb\0" \
- "fdt_addr_r=0x00700000\0" \
- "scriptaddr=0x00800000\0" \
- "pxefile_addr_r=0x00800000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "ramdisk_addr_r=0x00900000\0" \
+ "fdt_addr_r=0x00408000\0" \
+ "scriptaddr=0x00418000\0" \
+ "pxefile_addr_r=0x00428000\0" \
+ "ramdisk_addr_r=0x00438000\0" \
BOOTENV
/*
diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h
index 463f1c4..8212fb6 100644
--- a/include/configs/stm32f469-discovery.h
+++ b/include/configs/stm32f469-discovery.h
@@ -7,6 +7,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
+
+/* For booting Linux, use the first 12MB of memory */
+#define CONFIG_SYS_BOOTMAPSZ SZ_8M + SZ_4M
+
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
@@ -40,12 +45,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x00008000\0" \
"fdtfile=stm32f469-disco.dtb\0" \
- "fdt_addr_r=0x00700000\0" \
- "scriptaddr=0x00800000\0" \
- "pxefile_addr_r=0x00800000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "ramdisk_addr_r=0x00900000\0" \
+ "fdt_addr_r=0x00408000\0" \
+ "scriptaddr=0x00418000\0" \
+ "pxefile_addr_r=0x00428000\0" \
+ "ramdisk_addr_r=0x00438000\0" \
BOOTENV
/*
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 337b999..45343d2 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -7,6 +7,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <linux/sizes.h>
+
+/* For booting Linux, use the first 6MB of memory */
+#define CONFIG_SYS_BOOTMAPSZ SZ_4M + SZ_2M
+
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
@@ -48,12 +53,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xC0008000\0" \
"fdtfile=stm32f746-disco.dtb\0" \
- "fdt_addr_r=0xC0500000\0" \
- "scriptaddr=0xC0008000\0" \
- "pxefile_addr_r=0xC0008000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "ramdisk_addr_r=0xC0600000\0" \
+ "fdt_addr_r=0xC0408000\0" \
+ "scriptaddr=0xC0418000\0" \
+ "pxefile_addr_r=0xC0428000\0" \
+ "ramdisk_addr_r=0xC0438000\0" \
BOOTENV
/*
diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h
index 74c69eb..39c93ee 100644
--- a/include/configs/stm32h743-disco.h
+++ b/include/configs/stm32h743-disco.h
@@ -8,6 +8,10 @@
#define __CONFIG_H
#include <config.h>
+#include <linux/sizes.h>
+
+/* For booting Linux, use the first 16MB of memory */
+#define CONFIG_SYS_BOOTMAPSZ SZ_16M
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
@@ -35,12 +39,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xD0008000\0" \
"fdtfile=stm32h743i-disco.dtb\0" \
- "fdt_addr_r=0xD0700000\0" \
- "scriptaddr=0xD0800000\0" \
- "pxefile_addr_r=0xD0800000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "ramdisk_addr_r=0xD0900000\0" \
+ "fdt_addr_r=0xD0408000\0" \
+ "scriptaddr=0xD0418000\0" \
+ "pxefile_addr_r=0xD0428000\0" \
+ "ramdisk_addr_r=0xD0438000\0" \
BOOTENV
/*
diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h
index b7c8492..8eb94c1 100644
--- a/include/configs/stm32h743-eval.h
+++ b/include/configs/stm32h743-eval.h
@@ -8,6 +8,10 @@
#define __CONFIG_H
#include <config.h>
+#include <linux/sizes.h>
+
+/* For booting Linux, use the first 16MB of memory */
+#define CONFIG_SYS_BOOTMAPSZ SZ_16M
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x24040000
@@ -35,12 +39,10 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0xD0008000\0" \
"fdtfile=stm32h743i-eval.dtb\0" \
- "fdt_addr_r=0xD0700000\0" \
- "scriptaddr=0xD0800000\0" \
- "pxefile_addr_r=0xD0800000\0" \
- "fdt_high=0xffffffffffffffff\0" \
- "initrd_high=0xffffffffffffffff\0" \
- "ramdisk_addr_r=0xD0900000\0" \
+ "fdt_addr_r=0xD0408000\0" \
+ "scriptaddr=0xD0418000\0" \
+ "pxefile_addr_r=0xD0428000\0" \
+ "ramdisk_addr_r=0xD0438000\0" \
BOOTENV
/*
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index a66534e..42717c1 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -43,8 +43,14 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
+/*
+ * For booting Linux, use the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ SZ_256M
+
/* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN SZ_32M
+#define CONFIG_SYS_BOOTM_LEN SZ_32M
/* SPL support */
#ifdef CONFIG_SPL
@@ -215,8 +221,6 @@
"pxefile_addr_r=0xc4200000\0" \
"splashimage=0xc4300000\0" \
"ramdisk_addr_r=0xc4400000\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
"altbootcmd=run bootcmd\0" \
"env_default=1\0" \
"env_check=if test $env_default -eq 1;"\
diff --git a/tools/stm32image.c b/tools/stm32image.c
index ff3ec5f..18357c0 100644
--- a/tools/stm32image.c
+++ b/tools/stm32image.c
@@ -45,7 +45,7 @@
ptr->magic_number = HEADER_MAGIC;
ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1;
ptr->option_flags = HEADER_DEFAULT_OPTION;
- ptr->ecdsa_algorithm = 1;
+ ptr->ecdsa_algorithm = cpu_to_le32(1);
ptr->binary_type = HEADER_TYPE_UBOOT;
}
@@ -131,7 +131,8 @@
stm32hdr->image_entry_point = cpu_to_le32(params->ep);
stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size -
sizeof(struct stm32_header));
- stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
+ stm32hdr->image_checksum =
+ cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size));
}
/*