commit e45286a8bb25b97aac3dcf227eae899ffe8a1af3
author Mayuresh Chitale <mchitale@ventanamicro.com> Thu Nov 16 22:21:02 2023 +0530
committer Michal Simek <michal.simek@amd.com> Wed Dec 13 08:58:06 2023 +0100
tree 59152577c1c6cbfbd2142165db8f1257984c7378
parent 69e51047ec31a5ecfa9d2daf6ecd4e1238c35c60

pci: xilinx: Fix "reg" not found error

Fix the driver to use the dev_read_addr_size API to fetch the reg
property from the DT.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Link: https://lore.kernel.org/r/20231116165103.140968-2-mchitale@ventanamicro.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

drivers/pci/pcie_xilinx.c

diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c
index 53fd121..fdc9b08 100644
--- a/drivers/pci/pcie_xilinx.c
+++ b/drivers/pci/pcie_xilinx.c
@@ -8,11 +8,10 @@
 #include <common.h>
 #include <dm.h>
 #include <pci.h>
-#include <asm/global_data.h>
 #include <linux/bitops.h>
 #include <linux/printk.h>
-
-#include <asm/io.h>
+#include <linux/io.h>
+#include <linux/err.h>
 
 /**
  * struct xilinx_pcie - Xilinx PCIe controller state
@@ -140,20 +139,16 @@
 static int pcie_xilinx_of_to_plat(struct udevice *dev)
 {
 	struct xilinx_pcie *pcie = dev_get_priv(dev);
-	struct fdt_resource reg_res;
-	DECLARE_GLOBAL_DATA_PTR;
-	int err;
+	fdt_addr_t addr;
+	fdt_size_t size;
 
-	err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
-			       0, &reg_res);
-	if (err < 0) {
-		pr_err("\"reg\" resource not found\n");
-		return err;
-	}
+	addr = dev_read_addr_size(dev, &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
 
-	pcie->cfg_base = map_physmem(reg_res.start,
-				     fdt_resource_size(&reg_res),
-				     MAP_NOCACHE);
+	pcie->cfg_base = devm_ioremap(dev, addr, size);
+	if (IS_ERR(pcie->cfg_base))
+		return PTR_ERR(pcie->cfg_base);
 
 	return 0;
 }