| commit | b2ccd1cf71c2cec646525adb5025bde8206dbab9 | [log] [tgz] |
|---|---|---|
| author | Yu Chien Peter Lin <peterlin@andestech.com> | Mon Feb 06 16:10:49 2023 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Fri Feb 17 19:07:48 2023 +0800 |
| tree | 0974016a0055021ce694ff5785addaf3066602f0 | |
| parent | 5cc6b3f0e9099982001b0616a4ec3283be2cdbe6 [diff] |
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL This patch refines L1 cache enable/disable and v5l2-cache enable functions. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>