ARM: renesas: Rename arch-/mach-rmobile to arch-/mach-renesas
Rename arch-rmobile to arch-renesas and mach-rmobile to mach-renesas
because all the chips are made by Renesas, while only a subset of
them is from the R-Mobile line.
Use the following command to perform the rename, with manual move of
the directories using git mv and manual fix up to arch/arm/Makefile:
"
$ git grep -l '\<\(arch\|mach\)-rmobile\>' | \
xargs -I {} sed -i 's@\<\(arch\|mach\)-rmobile\>@\1-renesas@g' {}
$ sed -i 's@rmobile@renesas@' board/*/*/Kconfig
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
new file mode 100644
index 0000000..5aacc6f
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig
@@ -0,0 +1,99 @@
+if ARCH_RENESAS
+
+# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
+config RCAR_64
+ bool
+ select ARM64
+ select CMD_CACHE
+ select OF_BOARD_SETUP
+ select PHY
+ select PINCONF
+ select PINCTRL
+ select POSITION_INDEPENDENT
+ imply CMD_FS_UUID
+ imply CMD_GPT
+ imply CMD_MMC_SWRITE if MMC
+ imply CMD_UUID
+ imply SUPPORT_EMMC_RPMB if MMC
+
+choice
+ prompt "Target Renesas SoC select"
+ default RCAR_32
+
+config RCAR_32
+ bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
+ select CPU_V7A
+
+config RCAR_GEN3
+ bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
+ select RCAR_64
+ select SUPPORT_SPL
+ select PINCTRL_PFC
+ imply SPL
+ imply SPL_BOARD_INIT
+ imply SPL_GZIP
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_SERIAL
+ imply SPL_SYS_MALLOC_SIMPLE
+ imply SPL_TINY_MEMSET
+ imply SPL_USE_TINY_PRINTF
+ imply SPL_YMODEM_SUPPORT
+
+config RCAR_GEN4
+ bool "Renesas ARM SoCs R-Car Gen4 (64bit)"
+ select RCAR_64
+ select PINCTRL_PFC
+
+config RZA1
+ prompt "Renesas ARM SoCs RZ/A1 (32bit)"
+ select CPU_V7A
+
+config RZN1
+ prompt "Renesas ARM SoCs RZ/N1 (32bit)"
+ select CPU_V7A
+ select ARMV7_SET_CORTEX_SMPEN if !SPL
+ select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
+ select CLK
+ select CLK_RENESAS
+ select CLK_R9A06G032
+ select DM
+ select DM_ETH
+ select DM_SERIAL
+ select PINCTRL
+ select PINCONF
+ select REGMAP
+ select SYSRESET
+ select SYSRESET_SYSCON
+ imply CMD_DM
+
+config RZG2L
+ prompt "Renesas RZ/G2L Family ARM SoCs"
+ select GICV3
+ select RCAR_64
+ imply CLK_RZG2L
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply PINCTRL_RZG2L
+ imply RENESAS_SDHI
+ imply RZG2L_GPIO
+ imply SCIF_CONSOLE
+ imply SYS_MALLOC_F
+ help
+ Enable support for the Renesas RZ/G2L family of SoCs. Currently
+ support is only included for the RZ/G2L itself (based on the R9A07G044
+ SoC). Support for additional SoCs in this family (RZ/G2LC, RZ/G2UL,
+ RZ/V2L & RZ/Five) is not yet available.
+
+endchoice
+
+config SYS_SOC
+ default "renesas" if ARCH_RENESAS
+
+source "arch/arm/mach-renesas/Kconfig.32"
+source "arch/arm/mach-renesas/Kconfig.64"
+source "arch/arm/mach-renesas/Kconfig.rza1"
+source "arch/arm/mach-renesas/Kconfig.rzn1"
+source "arch/arm/mach-renesas/Kconfig.rzg2l"
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.32 b/arch/arm/mach-renesas/Kconfig.32
new file mode 100644
index 0000000..693a5ab
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.32
@@ -0,0 +1,160 @@
+if RCAR_32
+
+config ARCH_RENESAS_BOARD_STRING
+ string "Renesas RCar Gen2 board name"
+ default "Board"
+
+config RCAR_GEN2
+ bool "Renesas RCar Gen2"
+ select PHY
+ select PHY_RCAR_GEN2
+ select TMU_TIMER
+
+config R8A7790
+ bool "Renesas SoC R8A7790"
+ select RCAR_GEN2
+ select ARM_CORTEX_A15_CVE_2017_5715
+ imply CLK_R8A7790
+ imply PINCTRL_PFC_R8A7790
+
+config R8A7791
+ bool "Renesas SoC R8A7791"
+ select RCAR_GEN2
+ select ARM_CORTEX_A15_CVE_2017_5715
+ imply CLK_R8A7791
+ imply PINCTRL_PFC_R8A7791
+
+config R8A7792
+ bool "Renesas SoC R8A7792"
+ select RCAR_GEN2
+ select ARM_CORTEX_A15_CVE_2017_5715
+ imply CLK_R8A7792
+ imply PINCTRL_PFC_R8A7792
+
+config R8A7793
+ bool "Renesas SoC R8A7793"
+ select RCAR_GEN2
+ select ARM_CORTEX_A15_CVE_2017_5715
+ imply CLK_R8A7793
+ imply PINCTRL_PFC_R8A7793
+
+config R8A7794
+ bool "Renesas SoC R8A7794"
+ select RCAR_GEN2
+ imply CLK_R8A7794
+ imply PINCTRL_PFC_R8A7794
+
+choice
+ prompt "Renesas ARM SoCs board select"
+ optional
+
+config TARGET_BLANCHE
+ bool "Blanche board"
+ select DM
+ select DM_SERIAL
+ imply CMD_DM
+
+config TARGET_GOSE
+ bool "Gose board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+config TARGET_KOELSCH
+ bool "Koelsch board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+config TARGET_LAGER
+ bool "Lager board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+config TARGET_ALT
+ bool "Alt board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+config TARGET_SILK
+ bool "Silk board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+config TARGET_PORTER
+ bool "Porter board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+config TARGET_STOUT
+ bool "Stout board"
+ select DM
+ select DM_SERIAL
+ select SPL_TINY_MEMSET
+ select SUPPORT_SPL
+ select SPL_USE_TINY_PRINTF
+ imply CMD_DM
+
+endchoice
+
+config TMU_TIMER
+ bool
+
+config RENESAS_EXTRAM_BOOT
+ bool "Enable boot from RAM"
+ depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
+
+choice
+ prompt "Qos setting primary"
+ depends on TARGET_ALT || TARGET_BLANCHE || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
+ default QOS_PRI_NORMAL
+
+config QOS_PRI_NORMAL
+ bool "Non primary"
+ help
+ Select normal mode for QoS setting.
+
+config QOS_PRI_MEDIA
+ bool "Media primary"
+ help
+ Select multimedia primary mode for QoS setting.
+
+config QOS_PRI_GFX
+ bool "GFX primary"
+ help
+ Select GFX(graphics) primary mode for QoS setting.
+
+endchoice
+
+source "board/renesas/blanche/Kconfig"
+source "board/renesas/gose/Kconfig"
+source "board/renesas/koelsch/Kconfig"
+source "board/renesas/lager/Kconfig"
+source "board/renesas/alt/Kconfig"
+source "board/renesas/silk/Kconfig"
+source "board/renesas/porter/Kconfig"
+source "board/renesas/stout/Kconfig"
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.64 b/arch/arm/mach-renesas/Kconfig.64
new file mode 100644
index 0000000..b5067d0
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.64
@@ -0,0 +1,12 @@
+if RCAR_64
+
+config SYS_MALLOC_F_LEN
+ default 0x8000 if RCAR_64
+
+config OF_LIBFDT_OVERLAY
+ default y if RCAR_64
+
+source "arch/arm/mach-renesas/Kconfig.rcar3"
+source "arch/arm/mach-renesas/Kconfig.rcar4"
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.rcar3 b/arch/arm/mach-renesas/Kconfig.rcar3
new file mode 100644
index 0000000..ad35d10
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.rcar3
@@ -0,0 +1,200 @@
+if RCAR_GEN3
+
+menu "Select Target SoC"
+
+config R8A774A1
+ bool "Renesas SoC R8A774A1"
+ select GICV2
+ imply CLK_R8A774A1
+ imply PINCTRL_PFC_R8A774A1
+
+config R8A774B1
+ bool "Renesas SoC R8A774B1"
+ select GICV2
+ imply CLK_R8A774B1
+ imply PINCTRL_PFC_R8A774B1
+
+config R8A774C0
+ bool "Renesas SoC R8A774C0"
+ select GICV2
+ imply CLK_R8A774C0
+ imply PINCTRL_PFC_R8A774C0
+
+config R8A774E1
+ bool "Renesas SoC R8A774E1"
+ select GICV2
+ imply CLK_R8A774E1
+ imply PINCTRL_PFC_R8A774E1
+
+config R8A7795
+ bool "Renesas SoC R8A7795"
+ select GICV2
+ imply CLK_R8A7795
+ imply PINCTRL_PFC_R8A77951
+
+config R8A7796
+ bool "Renesas SoC R8A7796"
+ select GICV2
+ imply CLK_R8A77960
+ imply CLK_R8A77961
+ imply PINCTRL_PFC_R8A77960
+ imply PINCTRL_PFC_R8A77961
+
+config R8A77965
+ bool "Renesas SoC R8A77965"
+ select GICV2
+ imply CLK_R8A77965
+ imply PINCTRL_PFC_R8A77965
+
+config R8A77970
+ bool "Renesas SoC R8A77970"
+ select GICV2
+ imply CLK_R8A77970
+ imply PINCTRL_PFC_R8A77970
+
+config R8A77980
+ bool "Renesas SoC R8A77980"
+ select GICV2
+ imply CLK_R8A77980
+ imply PINCTRL_PFC_R8A77980
+
+config R8A77990
+ bool "Renesas SoC R8A77990"
+ select GICV2
+ imply CLK_R8A77990
+ imply PINCTRL_PFC_R8A77990
+
+config R8A77995
+ bool "Renesas SoC R8A77995"
+ select GICV2
+ imply CLK_R8A77995
+ imply PINCTRL_PFC_R8A77995
+
+config RZ_G2
+ bool "Renesas ARM SoCs RZ/G2 (64bit)"
+
+endmenu
+
+choice
+ prompt "Renesas ARM64 SoCs board select"
+ optional
+
+config TARGET_BEACON_RZG2M
+ bool "Beacon EmbeddedWorks RZ/G2 Dev Kit"
+ select PINCTRL_PFC_R8A774A1
+ select PINCTRL_PFC_R8A774B1
+ select PINCTRL_PFC_R8A774E1
+ select R8A774A1
+ select R8A774B1
+ select R8A774E1
+ select RZ_G2
+ imply CLK_CCF
+ imply CLK_VERSACLOCK
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+
+config TARGET_CONDOR
+ bool "Condor board"
+ imply R8A77980
+ help
+ Support for Renesas R-Car Gen3 Condor platform
+
+config TARGET_V3HSK
+ bool "V3HSK board"
+ help
+ Support for Renesas R-Car Gen3 V3HSK platform
+
+config TARGET_DRAAK
+ bool "Draak board"
+ imply R8A77995
+ help
+ Support for Renesas R-Car Gen3 Draak platform
+
+config TARGET_EAGLE
+ bool "Eagle board"
+ imply R8A77970
+ help
+ Support for Renesas R-Car Gen3 Eagle platform
+
+config TARGET_V3MSK
+ bool "V3MSK board"
+ help
+ Support for Renesas R-Car Gen3 V3MSK platform
+
+config TARGET_EBISU
+ bool "Ebisu board"
+ imply R8A77990
+ help
+ Support for Renesas R-Car Gen3 Ebisu platform
+
+config TARGET_HIHOPE_RZG2
+ bool "HiHope RZ/G2 board"
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply R8A774A1
+ imply R8A774B1
+ imply R8A774E1
+ imply RZ_G2
+ imply SYS_MALLOC_F
+ help
+ Support for RZG2 HiHope platform
+
+config TARGET_SILINUX_EK874
+ bool "Silicon Linux EK874 board"
+ imply R8A774C0
+ imply RZ_G2
+ help
+ Support for Silicon Linux EK874 platform
+
+config TARGET_SALVATOR_X
+ bool "Salvator-X board"
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply R8A7795
+ imply R8A7796
+ imply R8A77965
+ imply SYS_MALLOC_F
+ help
+ Support for Renesas R-Car Gen3 platform
+
+config TARGET_ULCB
+ bool "ULCB board"
+ imply MULTI_DTB_FIT
+ imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply R8A7795
+ imply R8A7796
+ imply R8A77965
+ imply SYS_MALLOC_F
+ help
+ Support for Renesas R-Car Gen3 ULCB platform
+
+endchoice
+
+source "board/renesas/condor/Kconfig"
+source "board/renesas/draak/Kconfig"
+source "board/renesas/eagle/Kconfig"
+source "board/renesas/ebisu/Kconfig"
+source "board/renesas/salvator-x/Kconfig"
+source "board/renesas/ulcb/Kconfig"
+source "board/renesas/v3hsk/Kconfig"
+source "board/renesas/v3msk/Kconfig"
+source "board/beacon/beacon-rzg2m/Kconfig"
+source "board/hoperun/hihope-rzg2/Kconfig"
+source "board/silinux/ek874/Kconfig"
+
+config MULTI_DTB_FIT_UNCOMPRESS_SZ
+ default 0x80000 if TARGET_BEACON_RZG2M
+ default 0x80000 if TARGET_HIHOPE_RZG2
+ default 0x80000 if TARGET_SALVATOR_X
+ default 0x80000 if TARGET_ULCB
+
+config MULTI_DTB_FIT_USER_DEF_ADDR
+ default 0x49000000 if TARGET_BEACON_RZG2M
+ default 0x49000000 if TARGET_HIHOPE_RZG2
+ default 0x49000000 if TARGET_SALVATOR_X
+ default 0x49000000 if TARGET_ULCB
+
+config DM_RESET
+ default y if RCAR_GEN3
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4
new file mode 100644
index 0000000..e80dce1
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.rcar4
@@ -0,0 +1,66 @@
+if RCAR_GEN4
+
+menu "Select Target SoC"
+
+config R8A779A0
+ bool "Renesas SoC R8A779A0"
+ select GICV3
+ imply CLK_R8A779A0
+ imply PINCTRL_PFC_R8A779A0
+
+config R8A779F0
+ bool "Renesas SoC R8A779F0"
+ select GICV3
+ imply CLK_R8A779F0
+ imply PINCTRL_PFC_R8A779F0
+
+config R8A779G0
+ bool "Renesas SoC R8A779G0"
+ select GICV3
+ imply CLK_R8A779G0
+ imply PINCTRL_PFC_R8A779G0
+
+config R8A779H0
+ bool "Renesas SoC R8A779H0"
+ select GICV3
+ imply CLK_R8A779H0
+ imply PINCTRL_PFC_R8A779H0
+
+endmenu
+
+choice
+ prompt "Renesas ARM64 SoCs board select"
+ optional
+
+config TARGET_FALCON
+ bool "Falcon board"
+ imply R8A779A0
+ help
+ Support for Renesas R-Car Gen3 Falcon platform
+
+config TARGET_SPIDER
+ bool "Spider board"
+ imply R8A779F0
+ help
+ Support for Renesas R-Car Gen4 Spider platform
+
+config TARGET_WHITEHAWK
+ bool "White Hawk board"
+ imply R8A779G0
+ help
+ Support for Renesas R-Car Gen4 White Hawk platform
+
+config TARGET_GRAYHAWK
+ bool "Gray Hawk board"
+ imply R8A779H0
+ help
+ Support for Renesas R-Car Gen4 Gray Hawk platform
+
+endchoice
+
+source "board/renesas/falcon/Kconfig"
+source "board/renesas/spider/Kconfig"
+source "board/renesas/whitehawk/Kconfig"
+source "board/renesas/grayhawk/Kconfig"
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.rza1 b/arch/arm/mach-renesas/Kconfig.rza1
new file mode 100644
index 0000000..e88f9a2
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.rza1
@@ -0,0 +1,25 @@
+if RZA1
+
+# required by the Ethernet driver
+config R7S72100
+ bool
+ default y
+
+# required by serial and usb driver
+config CPU_RZA1
+ bool
+ default y
+
+choice
+ prompt "Renesas RZ/A1 board select"
+
+# Renesas Supported Boards
+config TARGET_GRPEACH
+ bool "GR-PEACH board"
+
+endchoice
+
+# Renesas Supported Boards
+source "board/renesas/grpeach/Kconfig"
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.rzg2l b/arch/arm/mach-renesas/Kconfig.rzg2l
new file mode 100644
index 0000000..dc30bdf
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.rzg2l
@@ -0,0 +1,32 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+if RZG2L
+
+config R9A07G044L
+ bool "Renesas R9A07G044L SoC"
+ imply CLK_R9A07G044
+ help
+ Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.
+
+choice
+ prompt "Renesas RZ/G2L Family Board selection"
+ default TARGET_RZG2L_SMARC_EVK
+
+config TARGET_RZG2L_SMARC_EVK
+ bool "Renesas RZ/G2L SMARC EVK"
+ imply R9A07G044L
+ help
+ Enable support for the RZ/G2L SMARC evaluation board.
+
+source "board/renesas/rzg2l/Kconfig"
+
+endchoice
+
+config MULTI_DTB_FIT_UNCOMPRESS_SZ
+ default 0x80000 if TARGET_RZG2L_SMARC_EVK
+
+config MULTI_DTB_FIT_USER_DEF_ADDR
+ default 0x49000000 if TARGET_RZG2L_SMARC_EVK
+
+endif
diff --git a/arch/arm/mach-renesas/Kconfig.rzn1 b/arch/arm/mach-renesas/Kconfig.rzn1
new file mode 100644
index 0000000..73138d6
--- /dev/null
+++ b/arch/arm/mach-renesas/Kconfig.rzn1
@@ -0,0 +1,20 @@
+if RZN1
+
+choice
+ prompt "Renesas RZ/N1 Board select"
+ default TARGET_SCHNEIDER_RZN1
+
+config TARGET_SCHNEIDER_RZN1
+ bool "Schneider RZN1 board"
+ help
+ Support the Schneider RZN1D and RZN1S boards, which are based
+ on the Renesas RZ/N1 SoC.
+
+endchoice
+
+config SYS_SOC
+ default "rzn1"
+
+source "board/schneider/rzn1-snarc/Kconfig"
+
+endif
diff --git a/arch/arm/mach-renesas/Makefile b/arch/arm/mach-renesas/Makefile
new file mode 100644
index 0000000..71e12e0
--- /dev/null
+++ b/arch/arm/mach-renesas/Makefile
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-y = cpu_info.o
+obj-y += emac.o
+
+obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
+obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
+obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
+obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o
+
+ifneq ($(CONFIG_R8A779A0),)
+obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
+endif
+
+OBJCOPYFLAGS_u-boot-spl.srec := -O srec
+quiet_cmd_objcopy = OBJCOPY $@
+cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \
+ $(OBJCOPYFLAGS_$(@F)) $< $@
+
+spl/u-boot-spl.srec: spl/u-boot-spl FORCE
+ $(call if_changed,objcopy)
+
+srec_cat_gte_160 := ${shell expr `srec_cat -VERSION | grep ^srec_cat | sed 's/^.* //g' | cut -f1-2 -d.` \>= "1.60"}
+ifeq "$(srec_cat_gte_160)" "1"
+ srec_cat_le_cmd := "-constant-l-e"
+else
+ srec_cat_le_cmd := "-l-e-constant"
+endif
+
+ifneq ($(CONFIG_R8A774C0)$(CONFIG_R8A77990)$(CONFIG_R8A77995),)
+#
+# The first 6 generate statements generate the R-Car Gen3 SCIF loader header.
+# The subsequent generate statements represent the following chunk of assembler
+# code, which copies the loaded data from 0xe6304030 to 0xe6318000. This is to
+# work around a limitation of the D3/E3 BootROM, which does not permit loading
+# to 0xe6318000 directly.
+#
+# mov x0, #0xe6000000
+# orr x0, x0, #0x00300000
+# orr x1, x0, #0x00004000
+# orr x1, x1, #0x00000030
+#
+# orr x2, x0, #0x00018000
+# mov x0, x2
+# mov x3, #0x7000
+#1: ldp x4, x5, [x1], #16
+#
+# stp x4, x5, [x2], #16
+# subs x3, x3, #16
+# b.ge 1b
+# br x0
+#
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+ -offset -0x13fd0 \
+ -Output_Block_Size 16 \
+ -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) 0xe6304000 4 \
+ -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \
+ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) 0xe6304000 4 \
+ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4 \
+ -generate 0xe6304000 0xe6304004 $(srec_cat_le_cmd) 0xd2bcc000 4 \
+ -generate 0xe6304004 0xe6304008 $(srec_cat_le_cmd) 0xb26c0400 4 \
+ -generate 0xe6304008 0xe630400c $(srec_cat_le_cmd) 0xb2720001 4 \
+ -generate 0xe630400c 0xe6304010 $(srec_cat_le_cmd) 0xb27c0421 4 \
+ -generate 0xe6304010 0xe6304014 $(srec_cat_le_cmd) 0xb2710402 4 \
+ -generate 0xe6304014 0xe6304018 $(srec_cat_le_cmd) 0xaa0203e0 4 \
+ -generate 0xe6304018 0xe630401c $(srec_cat_le_cmd) 0xd28e0003 4 \
+ -generate 0xe630401c 0xe6304020 $(srec_cat_le_cmd) 0xa8c11424 4 \
+ -generate 0xe6304020 0xe6304024 $(srec_cat_le_cmd) 0xa8811444 4 \
+ -generate 0xe6304024 0xe6304028 $(srec_cat_le_cmd) 0xf1004063 4 \
+ -generate 0xe6304028 0xe630402c $(srec_cat_le_cmd) 0x54ffffaa 4 \
+ -generate 0xe630402c 0xe6304030 $(srec_cat_le_cmd) 0xd61f0000 4
+else
+quiet_cmd_srec_cat = SRECCAT $@
+ cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
+ -Output_Block_Size 16 \
+ -generate 0xe6300400 0xe6300404 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe630048c 0xe6300490 $(srec_cat_le_cmd) 0x0 4 \
+ -generate 0xe63005d4 0xe63005d8 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe63006e4 0xe63006e8 $(srec_cat_le_cmd) $2 4 \
+ -generate 0xe6301154 0xe6301158 $(srec_cat_le_cmd) $(CONFIG_SPL_TEXT_BASE) 4 \
+ -generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
+endif
+
+spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
+ $(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
+
+# if srec_cat is present build u-boot-spl.scif by default
+has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
+INPUTS-$(has_srec_cat) += u-boot-spl.scif
+CLEAN_FILES += u-boot-spl.scif
diff --git a/arch/arm/mach-renesas/board.c b/arch/arm/mach-renesas/board.c
new file mode 100644
index 0000000..f061e41
--- /dev/null
+++ b/arch/arm/mach-renesas/board.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ */
+
+#include <init.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_ARCH_RENESAS_BOARD_STRING
+int checkboard(void)
+{
+ printf("Board: %s\n", CONFIG_ARCH_RENESAS_BOARD_STRING);
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-renesas/cpu_info-rcar.c b/arch/arm/mach-renesas/cpu_info-rcar.c
new file mode 100644
index 0000000..9418836
--- /dev/null
+++ b/arch/arm/mach-renesas/cpu_info-rcar.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ */
+
+#include <asm/io.h>
+
+#define PRR_MASK 0x7fff
+#define R8A7796_REV_1_0 0x5200
+#define R8A7796_REV_1_1 0x5210
+#define R8A7796_REV_1_3 0x5211
+#define R8A77995_REV_1_1 0x5810
+
+static u32 renesas_get_prr(void)
+{
+ if (IS_ENABLED(CONFIG_RCAR_64))
+ return readl(0xFFF00044);
+
+ return readl(0xFF000044);
+}
+
+u32 renesas_get_cpu_type(void)
+{
+ return (renesas_get_prr() & 0x00007F00) >> 8;
+}
+
+u32 renesas_get_cpu_rev_integer(void)
+{
+ const u32 prr = renesas_get_prr();
+ const u32 rev = prr & PRR_MASK;
+
+ if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3 ||
+ rev == R8A77995_REV_1_1)
+ return 1;
+ else
+ return ((prr & 0x000000F0) >> 4) + 1;
+}
+
+u32 renesas_get_cpu_rev_fraction(void)
+{
+ const u32 prr = renesas_get_prr();
+ const u32 rev = prr & PRR_MASK;
+
+ if (rev == R8A7796_REV_1_1 || rev == R8A77995_REV_1_1)
+ return 1;
+ else if (rev == R8A7796_REV_1_3)
+ return 3;
+ else
+ return prr & 0x0000000F;
+}
diff --git a/arch/arm/mach-renesas/cpu_info-rzg.c b/arch/arm/mach-renesas/cpu_info-rzg.c
new file mode 100644
index 0000000..4ade4bc
--- /dev/null
+++ b/arch/arm/mach-renesas/cpu_info-rzg.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Renesas Electronics Corporation
+ *
+ */
+
+#include <linux/libfdt.h>
+
+/* If the firmware passed a device tree, use it for soc identification. */
+extern u64 rcar_atf_boot_args[];
+
+/* CPU information table */
+static const struct {
+ char *soc_name;
+ u8 cpu_name[10];
+} tfa_info[] = {
+ { "renesas,r8a774a1", "R8A774A1" },
+ { "renesas,r8a774b1", "R8A774B1" },
+ { "renesas,r8a774c0", "R8A774C0" },
+ { "renesas,r8a774e1", "R8A774E1" }
+};
+
+const u8 *rzg_get_cpu_name(void)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+ bool ret = false;
+ int i;
+
+ if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+ return NULL;
+
+ for (i = 0; i < ARRAY_SIZE(tfa_info); i++) {
+ if (fdt_node_check_compatible(atf_fdt_blob, 0,
+ tfa_info[i].soc_name) == 0) {
+ ret = true;
+ break;
+ }
+ }
+
+ return ret ? tfa_info[i].cpu_name : NULL;
+}
diff --git a/arch/arm/mach-renesas/cpu_info-rzg2l.c b/arch/arm/mach-renesas/cpu_info-rzg2l.c
new file mode 100644
index 0000000..ab95ce7
--- /dev/null
+++ b/arch/arm/mach-renesas/cpu_info-rzg2l.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021,2023 Renesas Electronics Corporation
+ *
+ */
+
+#include <mach/renesas.h>
+#include <asm/io.h>
+#include <linux/libfdt.h>
+
+#define SYSC_LSI_DEVID 0x11020A04
+
+/* If the firmware passed a device tree, use it for soc identification. */
+extern u64 rcar_atf_boot_args[];
+
+/* CPU information table */
+struct tfa_info {
+ const char *soc_name;
+ const char *cpu_name;
+ u32 cpu_type;
+};
+
+static const struct tfa_info tfa_info[] = {
+ { "renesas,r9a07g044l2", "R9A07G044L", RENESAS_CPU_TYPE_R9A07G044L },
+};
+
+static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 };
+
+static const struct tfa_info *get_tfa_info(void)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) {
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE(tfa_info); i++) {
+ if (!fdt_node_check_compatible(atf_fdt_blob, 0,
+ tfa_info[i].soc_name))
+ return &tfa_info[i];
+ }
+ }
+
+ return &invalid_tfa_info;
+}
+
+const u8 *rzg_get_cpu_name(void)
+{
+ return get_tfa_info()->cpu_name;
+}
+
+u32 renesas_get_cpu_type(void)
+{
+ return get_tfa_info()->cpu_type;
+}
+
+u32 renesas_get_cpu_rev_integer(void)
+{
+ return (readl(SYSC_LSI_DEVID) >> 28) + 1;
+}
+
+u32 renesas_get_cpu_rev_fraction(void)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-renesas/cpu_info.c b/arch/arm/mach-renesas/cpu_info.c
new file mode 100644
index 0000000..2f9a437
--- /dev/null
+++ b/arch/arm/mach-renesas/cpu_info.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012-2021 Renesas Solutions Corp.
+ */
+
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <init.h>
+#include <asm/io.h>
+#include <env.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ icache_enable();
+ return 0;
+}
+#endif
+
+/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */
+#ifndef CONFIG_RCAR_64
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+ dcache_enable();
+}
+#endif
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1)
+__weak const u8 *rzg_get_cpu_name(void)
+{
+ return 0;
+}
+
+__weak u32 renesas_get_cpu_type(void)
+{
+ return 0x0;
+}
+
+__weak u32 renesas_get_cpu_rev_integer(void)
+{
+ return 0;
+}
+
+__weak u32 renesas_get_cpu_rev_fraction(void)
+{
+ return 0;
+}
+
+/* CPU information table */
+static const struct {
+ u16 cpu_type;
+ u8 cpu_name[10];
+} renesas_cpuinfo[] = {
+ { RENESAS_CPU_TYPE_R8A7790, "R8A7790" },
+ { RENESAS_CPU_TYPE_R8A7791, "R8A7791" },
+ { RENESAS_CPU_TYPE_R8A7792, "R8A7792" },
+ { RENESAS_CPU_TYPE_R8A7793, "R8A7793" },
+ { RENESAS_CPU_TYPE_R8A7794, "R8A7794" },
+ { RENESAS_CPU_TYPE_R8A7795, "R8A7795" },
+ { RENESAS_CPU_TYPE_R8A7796, "R8A7796" },
+ { RENESAS_CPU_TYPE_R8A77965, "R8A77965" },
+ { RENESAS_CPU_TYPE_R8A77970, "R8A77970" },
+ { RENESAS_CPU_TYPE_R8A77980, "R8A77980" },
+ { RENESAS_CPU_TYPE_R8A77990, "R8A77990" },
+ { RENESAS_CPU_TYPE_R8A77995, "R8A77995" },
+ { RENESAS_CPU_TYPE_R8A779A0, "R8A779A0" },
+ { RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" },
+ { RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" },
+ { RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" },
+ { 0x0, "CPU" },
+};
+
+static int renesas_cpuinfo_idx(void)
+{
+ u32 cpu_type = renesas_get_cpu_type();
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(renesas_cpuinfo) - 1; i++)
+ if (renesas_cpuinfo[i].cpu_type == cpu_type)
+ return i;
+
+ /* Unknown "CPU" entry */
+ return ARRAY_SIZE(renesas_cpuinfo) - 1;
+}
+
+static const u8 *get_cpu_name(int idx)
+{
+ const u8 *cpu_name = rzg_get_cpu_name();
+
+ return cpu_name ? cpu_name : renesas_cpuinfo[idx].cpu_name;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ int i, idx = renesas_cpuinfo_idx();
+ const u8 *cpu_name = get_cpu_name(idx);
+ char cpu[10] = { 0 };
+
+ for (i = 0; i < sizeof(cpu); i++)
+ cpu[i] = tolower(cpu_name[i]);
+
+ env_set("platform", cpu);
+
+ return 0;
+}
+#endif
+
+int print_cpuinfo(void)
+{
+ int i = renesas_cpuinfo_idx();
+
+ if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 &&
+ renesas_get_cpu_rev_integer() == 1 &&
+ renesas_get_cpu_rev_fraction() == 1) {
+ printf("CPU: Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i));
+ return 0;
+ }
+
+ printf("CPU: Renesas Electronics %s rev %d.%d\n",
+ get_cpu_name(i), renesas_get_cpu_rev_integer(),
+ renesas_get_cpu_rev_fraction());
+
+ return 0;
+}
+#elif defined(CONFIG_RZA1)
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/A1\n");
+ return 0;
+}
+#else /* CONFIG_RZN1 */
+int print_cpuinfo(void)
+{
+ printf("CPU: Renesas Electronics RZ/N1\n");
+ return 0;
+}
+#endif
+#endif /* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/mach-renesas/emac.c b/arch/arm/mach-renesas/emac.c
new file mode 100644
index 0000000..9565162
--- /dev/null
+++ b/arch/arm/mach-renesas/emac.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RMOBILE EtherMAC initialization.
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ */
+
+#include <net.h>
+#include <linux/errno.h>
+#include <netdev.h>
+
+int cpu_eth_init(struct bd_info *bis)
+{
+ int ret = -ENODEV;
+#ifdef CONFIG_SH_ETHER
+ ret = sh_eth_initialize(bis);
+#endif
+ return ret;
+}
diff --git a/arch/arm/mach-renesas/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h
new file mode 100644
index 0000000..1d8c3ee
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/boot0.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Specialty padding for the RCar Gen2 SPL JTAG loading
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+_start:
+ ARM_VECTORS
+
+#ifdef CONFIG_SPL_BUILD
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+ .word 0x0badc0d3;
+#endif
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/mach-renesas/include/mach/gpio.h b/arch/arm/mach-renesas/include/mach/gpio.h
new file mode 100644
index 0000000..efdde0a
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/gpio.h
@@ -0,0 +1,4 @@
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-renesas/include/mach/irqs.h b/arch/arm/mach-renesas/include/mach/irqs.h
new file mode 100644
index 0000000..dcb714f
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/irqs.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_MACH_IRQS_H
+#define __ASM_MACH_IRQS_H
+
+#define NR_IRQS 1024
+
+/* GIC */
+#define gic_spi(nr) ((nr) + 32)
+
+/* INTCA */
+#define evt2irq(evt) (((evt) >> 5) - 16)
+#define irq2evt(irq) (((irq) + 16) << 5)
+
+/* INTCS */
+#define INTCS_VECT_BASE 0x2200
+#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
+#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
+
+#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-renesas/include/mach/r8a7790.h b/arch/arm/mach-renesas/include/mach/r8a7790.h
new file mode 100644
index 0000000..61101df
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/r8a7790.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/r8a7790.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_R8A7790_H
+#define __ASM_ARCH_R8A7790_H
+
+#include "rcar-base.h"
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00640801
+#define MSTP1_BITS 0xDB6E9BDF
+#define MSTP2_BITS 0x300DA1FC
+#define MSTP3_BITS 0xF08CF831
+#define MSTP4_BITS 0x80000184
+#define MSTP5_BITS 0x44C00046
+#define MSTP7_BITS 0x07F30718
+#define MSTP8_BITS 0x01F0FF84
+#define MSTP9_BITS 0xF5979FCF
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x00000000
+
+/* SDHI */
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 4
+
+#define R8A7790_CUT_ES2X 2
+#define IS_R8A7790_ES2() \
+ (renesas_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
+
+#endif /* __ASM_ARCH_R8A7790_H */
diff --git a/arch/arm/mach-renesas/include/mach/r8a7791.h b/arch/arm/mach-renesas/include/mach/r8a7791.h
new file mode 100644
index 0000000..40524d7
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/r8a7791.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/r8a7791.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_R8A7791_H
+#define __ASM_ARCH_R8A7791_H
+
+#include "rcar-base.h"
+/*
+ * R-Car (R8A7791) I/O Addresses
+ */
+
+/* SDHI */
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
+
+#define DBSC3_1_QOS_R0_BASE 0xE67A1000
+#define DBSC3_1_QOS_R1_BASE 0xE67A1100
+#define DBSC3_1_QOS_R2_BASE 0xE67A1200
+#define DBSC3_1_QOS_R3_BASE 0xE67A1300
+#define DBSC3_1_QOS_R4_BASE 0xE67A1400
+#define DBSC3_1_QOS_R5_BASE 0xE67A1500
+#define DBSC3_1_QOS_R6_BASE 0xE67A1600
+#define DBSC3_1_QOS_R7_BASE 0xE67A1700
+#define DBSC3_1_QOS_R8_BASE 0xE67A1800
+#define DBSC3_1_QOS_R9_BASE 0xE67A1900
+#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE 0xE67A2000
+#define DBSC3_1_QOS_W1_BASE 0xE67A2100
+#define DBSC3_1_QOS_W2_BASE 0xE67A2200
+#define DBSC3_1_QOS_W3_BASE 0xE67A2300
+#define DBSC3_1_QOS_W4_BASE 0xE67A2400
+#define DBSC3_1_QOS_W5_BASE 0xE67A2500
+#define DBSC3_1_QOS_W6_BASE 0xE67A2600
+#define DBSC3_1_QOS_W7_BASE 0xE67A2700
+#define DBSC3_1_QOS_W8_BASE 0xE67A2800
+#define DBSC3_1_QOS_W9_BASE 0xE67A2900
+#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
+#define DBSC3_1_DBADJ2 0xE67A00C8
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00640801
+#define MSTP1_BITS 0x9B6C9B5A
+#define MSTP2_BITS 0x100D21FC
+#define MSTP3_BITS 0xF08CD810
+#define MSTP4_BITS 0x800001C4
+#define MSTP5_BITS 0x44C00046
+#define MSTP7_BITS 0x05BFE618
+#define MSTP8_BITS 0x40C0FE85
+#define MSTP9_BITS 0xFF979FFF
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x000001C0
+
+#define R8A7791_CUT_ES2X 2
+#define IS_R8A7791_ES2() \
+ (renesas_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
+
+#endif /* __ASM_ARCH_R8A7791_H */
diff --git a/arch/arm/mach-renesas/include/mach/r8a7792.h b/arch/arm/mach-renesas/include/mach/r8a7792.h
new file mode 100644
index 0000000..51c0d63
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/r8a7792.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/r8a7792.h
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_R8A7792_H
+#define __ASM_ARCH_R8A7792_H
+
+#include "rcar-base.h"
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00400801
+#define MSTP1_BITS 0x9B6F987F
+#define MSTP2_BITS 0x108CE100
+#define MSTP3_BITS 0x20004010
+#define MSTP4_BITS 0x80000184
+#define MSTP5_BITS 0x44C00004
+#define MSTP7_BITS 0x01BF0000
+#define MSTP8_BITS 0x1FE01FB0
+#define MSTP9_BITS 0xFE2BFFB2
+#define MSTP10_BITS 0x00001820
+#define MSTP11_BITS 0x00000008
+
+/* SDHI */
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 1
+
+#endif /* __ASM_ARCH_R8A7792_H */
diff --git a/arch/arm/mach-renesas/include/mach/r8a7793.h b/arch/arm/mach-renesas/include/mach/r8a7793.h
new file mode 100644
index 0000000..f15f823
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/r8a7793.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/r8a7793.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_R8A7793_H
+#define __ASM_ARCH_R8A7793_H
+
+#include "rcar-base.h"
+
+/*
+ * R8A7793 I/O Addresses
+ */
+
+/* SDHI */
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
+
+#define DBSC3_1_QOS_R0_BASE 0xE67A1000
+#define DBSC3_1_QOS_R1_BASE 0xE67A1100
+#define DBSC3_1_QOS_R2_BASE 0xE67A1200
+#define DBSC3_1_QOS_R3_BASE 0xE67A1300
+#define DBSC3_1_QOS_R4_BASE 0xE67A1400
+#define DBSC3_1_QOS_R5_BASE 0xE67A1500
+#define DBSC3_1_QOS_R6_BASE 0xE67A1600
+#define DBSC3_1_QOS_R7_BASE 0xE67A1700
+#define DBSC3_1_QOS_R8_BASE 0xE67A1800
+#define DBSC3_1_QOS_R9_BASE 0xE67A1900
+#define DBSC3_1_QOS_R10_BASE 0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE 0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE 0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE 0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE 0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE 0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE 0xE67A2000
+#define DBSC3_1_QOS_W1_BASE 0xE67A2100
+#define DBSC3_1_QOS_W2_BASE 0xE67A2200
+#define DBSC3_1_QOS_W3_BASE 0xE67A2300
+#define DBSC3_1_QOS_W4_BASE 0xE67A2400
+#define DBSC3_1_QOS_W5_BASE 0xE67A2500
+#define DBSC3_1_QOS_W6_BASE 0xE67A2600
+#define DBSC3_1_QOS_W7_BASE 0xE67A2700
+#define DBSC3_1_QOS_W8_BASE 0xE67A2800
+#define DBSC3_1_QOS_W9_BASE 0xE67A2900
+#define DBSC3_1_QOS_W10_BASE 0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE 0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE 0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE 0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE 0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE 0xE67A2F00
+
+#define DBSC3_1_DBADJ2 0xE67A00C8
+
+/*
+ * R8A7793 I/O Product Information
+ */
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00640801
+#define MSTP1_BITS 0x9B6C9B5A
+#define MSTP2_BITS 0x100D21FC
+#define MSTP3_BITS 0xF08CD810
+#define MSTP4_BITS 0x800001C4
+#define MSTP5_BITS 0x44C00046
+#define MSTP7_BITS 0x05BFE618
+#define MSTP8_BITS 0x40C0FE85
+#define MSTP9_BITS 0xFF979FFF
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x000001C0
+
+#define R8A7793_CUT_ES2X 2
+#define IS_R8A7793_ES2() \
+ (renesas_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
+
+#endif /* __ASM_ARCH_R8A7793_H */
diff --git a/arch/arm/mach-renesas/include/mach/r8a7794.h b/arch/arm/mach-renesas/include/mach/r8a7794.h
new file mode 100644
index 0000000..592625e
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/r8a7794.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/r8a7794.h
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_R8A7794_H
+#define __ASM_ARCH_R8A7794_H
+
+#include "rcar-base.h"
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS 0x00440801
+#define MSTP1_BITS 0x936899DA
+#define MSTP2_BITS 0x100D21FC
+#define MSTP3_BITS 0xE084D810
+#define MSTP4_BITS 0x800001C4
+#define MSTP5_BITS 0x40C00044
+#define MSTP7_BITS 0x013FE618
+#define MSTP8_BITS 0x40803C05
+#define MSTP9_BITS 0xFB879FEE
+#define MSTP10_BITS 0xFFFEFFE0
+#define MSTP11_BITS 0x000001C0
+
+/* SDHI */
+#define CFG_SYS_SH_SDHI_NR_CHANNEL 3
+
+#define R8A7794_CUT_ES2 2
+#define IS_R8A7794_ES2() \
+ (renesas_get_cpu_rev_integer() == R8A7794_CUT_ES2)
+
+#endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/mach-renesas/include/mach/rcar-base.h b/arch/arm/mach-renesas/include/mach/rcar-base.h
new file mode 100644
index 0000000..4c2ee81
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/rcar-base.h
@@ -0,0 +1,1029 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/rcar-base.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_RCAR_BASE_H
+#define __ASM_ARCH_RCAR_BASE_H
+
+/*
+ * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
+ */
+#define RWDT_BASE 0xE6020000
+#define SWDT_BASE 0xE6030000
+#define LBSC_BASE 0xFEC00200
+#define DBSC3_0_BASE 0xE6790000
+#define DBSC3_1_BASE 0xE67A0000
+#define TMU_BASE 0xE61E0000
+#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
+
+/* SCIF */
+#define SCIF0_BASE 0xE6E60000
+#define SCIF1_BASE 0xE6E68000
+#define SCIF2_BASE 0xE6E58000
+#define SCIF3_BASE 0xE6EA8000
+#define SCIF4_BASE 0xE6EE0000
+#define SCIF5_BASE 0xE6EE8000
+#define SCIFA0_BASE 0xE6C40000
+#define SCIFA1_BASE 0xE6C50000
+#define SCIFA2_BASE 0xE6C60000
+
+/* Module stop status register */
+#define MSTPSR0 0xE6150030
+#define MSTPSR1 0xE6150038
+#define MSTPSR2 0xE6150040
+#define MSTPSR3 0xE6150048
+#define MSTPSR4 0xE615004C
+#define MSTPSR5 0xE615003C
+#define MSTPSR7 0xE61501C4
+#define MSTPSR8 0xE61509A0
+#define MSTPSR9 0xE61509A4
+#define MSTPSR10 0xE61509A8
+#define MSTPSR11 0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0 0xE6150110
+#define RMSTPCR1 0xE6150114
+#define RMSTPCR2 0xE6150118
+#define RMSTPCR3 0xE615011C
+#define RMSTPCR4 0xE6150120
+#define RMSTPCR5 0xE6150124
+#define RMSTPCR7 0xE615012C
+#define RMSTPCR8 0xE6150980
+#define RMSTPCR9 0xE6150984
+#define RMSTPCR10 0xE6150988
+#define RMSTPCR11 0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0 0xE6150130
+#define SMSTPCR1 0xE6150134
+#define SMSTPCR2 0xE6150138
+#define SMSTPCR3 0xE615013C
+#define SMSTPCR4 0xE6150140
+#define SMSTPCR5 0xE6150144
+#define SMSTPCR7 0xE615014C
+#define SMSTPCR8 0xE6150990
+#define SMSTPCR9 0xE6150994
+#define SMSTPCR10 0xE6150998
+#define SMSTPCR11 0xE615099C
+
+#define S3C_BASE 0xE6784000
+#define S3C_INT_BASE 0xE6784A00
+#define S3C_MEDIA_BASE 0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE 0xE6784BDC
+#define S3C_QOS_CCI0_BASE 0xE6784C00
+#define S3C_QOS_CCI1_BASE 0xE6784C24
+#define S3C_QOS_MXI_BASE 0xE6784C48
+#define S3C_QOS_AXI_BASE 0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE 0xE6791000
+#define DBSC3_0_QOS_R1_BASE 0xE6791100
+#define DBSC3_0_QOS_R2_BASE 0xE6791200
+#define DBSC3_0_QOS_R3_BASE 0xE6791300
+#define DBSC3_0_QOS_R4_BASE 0xE6791400
+#define DBSC3_0_QOS_R5_BASE 0xE6791500
+#define DBSC3_0_QOS_R6_BASE 0xE6791600
+#define DBSC3_0_QOS_R7_BASE 0xE6791700
+#define DBSC3_0_QOS_R8_BASE 0xE6791800
+#define DBSC3_0_QOS_R9_BASE 0xE6791900
+#define DBSC3_0_QOS_R10_BASE 0xE6791A00
+#define DBSC3_0_QOS_R11_BASE 0xE6791B00
+#define DBSC3_0_QOS_R12_BASE 0xE6791C00
+#define DBSC3_0_QOS_R13_BASE 0xE6791D00
+#define DBSC3_0_QOS_R14_BASE 0xE6791E00
+#define DBSC3_0_QOS_R15_BASE 0xE6791F00
+#define DBSC3_0_QOS_W0_BASE 0xE6792000
+#define DBSC3_0_QOS_W1_BASE 0xE6792100
+#define DBSC3_0_QOS_W2_BASE 0xE6792200
+#define DBSC3_0_QOS_W3_BASE 0xE6792300
+#define DBSC3_0_QOS_W4_BASE 0xE6792400
+#define DBSC3_0_QOS_W5_BASE 0xE6792500
+#define DBSC3_0_QOS_W6_BASE 0xE6792600
+#define DBSC3_0_QOS_W7_BASE 0xE6792700
+#define DBSC3_0_QOS_W8_BASE 0xE6792800
+#define DBSC3_0_QOS_W9_BASE 0xE6792900
+#define DBSC3_0_QOS_W10_BASE 0xE6792A00
+#define DBSC3_0_QOS_W11_BASE 0xE6792B00
+#define DBSC3_0_QOS_W12_BASE 0xE6792C00
+#define DBSC3_0_QOS_W13_BASE 0xE6792D00
+#define DBSC3_0_QOS_W14_BASE 0xE6792E00
+#define DBSC3_0_QOS_W15_BASE 0xE6792F00
+#define DBSC3_0_DBADJ2 0xE67900C8
+
+#define CCI_400_MAXOT_1 0xF0091110
+#define CCI_400_MAXOT_2 0xF0092110
+#define CCI_400_QOSCNTL_1 0xF009110C
+#define CCI_400_QOSCNTL_2 0xF009210C
+
+#define MXI_BASE 0xFE960000
+#define MXI_QOS_BASE 0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE 0xFF800300
+#define SYS_AXI_AVB_BASE 0xFF800340
+#define SYS_AXI_AX2M_BASE 0xFF800380
+#define SYS_AXI_CC50_BASE 0xFF8003C0
+#define SYS_AXI_CCI_BASE 0xFF800440
+#define SYS_AXI_CS_BASE 0xFF800480
+#define SYS_AXI_DDM_BASE 0xFF8004C0
+#define SYS_AXI_ETH_BASE 0xFF800500
+#define SYS_AXI_G2D_BASE 0xFF800540
+#define SYS_AXI_IMP0_BASE 0xFF800580
+#define SYS_AXI_IMP1_BASE 0xFF8005C0
+#define SYS_AXI_IMUX0_BASE 0xFF800600
+#define SYS_AXI_IMUX1_BASE 0xFF800640
+#define SYS_AXI_IMUX2_BASE 0xFF800680
+#define SYS_AXI_LBS_BASE 0xFF8006C0
+#define SYS_AXI_MMUDS_BASE 0xFF800700
+#define SYS_AXI_MMUM_BASE 0xFF800740
+#define SYS_AXI_MMUR_BASE 0xFF800780
+#define SYS_AXI_MMUS0_BASE 0xFF8007C0
+#define SYS_AXI_MMUS1_BASE 0xFF800800
+#define SYS_AXI_MPXM_BASE 0xFF800840
+#define SYS_AXI_MTSB0_BASE 0xFF800880
+#define SYS_AXI_MTSB1_BASE 0xFF8008C0
+#define SYS_AXI_PCI_BASE 0xFF800900
+#define SYS_AXI_RTX_BASE 0xFF800940
+#define SYS_AXI_SAT0_BASE 0xFF800980
+#define SYS_AXI_SAT1_BASE 0xFF8009C0
+#define SYS_AXI_SDM0_BASE 0xFF800A00
+#define SYS_AXI_SDM1_BASE 0xFF800A40
+#define SYS_AXI_SDS0_BASE 0xFF800A80
+#define SYS_AXI_SDS1_BASE 0xFF800AC0
+#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
+#define SYS_AXI_UDM0_BASE 0xFF800B80
+#define SYS_AXI_UDM1_BASE 0xFF800BC0
+#define SYS_AXI_USB20_BASE 0xFF800C00
+#define SYS_AXI_USB21_BASE 0xFF800C40
+#define SYS_AXI_USB22_BASE 0xFF800C80
+#define SYS_AXI_USB30_BASE 0xFF800CC0
+#define SYS_AXI_ADM_BASE 0xFF800D00
+#define SYS_AXI_ADS_BASE 0xFF800D40
+#define SYS_AXI_SYX_BASE 0xFF800FB8
+
+#define SYS_AXI_AXI64TO128W_BASE 0xFF801300
+#define SYS_AXI_AVBW_BASE 0xFF801340
+#define SYS_AXI_CC50W_BASE 0xFF8013C0
+#define SYS_AXI_CCIW_BASE 0xFF801440
+#define SYS_AXI_CSW_BASE 0xFF801480
+#define SYS_AXI_G2DW_BASE 0xFF801540
+#define SYS_AXI_IMUX0W_BASE 0xFF801600
+#define SYS_AXI_IMUX1W_BASE 0xFF801640
+#define SYS_AXI_IMUX2W_BASE 0xFF801680
+#define SYS_AXI_LBSW_BASE 0xFF8016C0
+#define SYS_AXI_RTXW_BASE 0xFF801940
+#define SYS_AXI_SDM0W_BASE 0xFF801A00
+#define SYS_AXI_SDM1W_BASE 0xFF801A40
+#define SYS_AXI_SDS0W_BASE 0xFF801A80
+#define SYS_AXI_SDS1W_BASE 0xFF801AC0
+#define SYS_AXI_TRABW_BASE 0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
+#define SYS_AXI_UDM0W_BASE 0xFF801B80
+#define SYS_AXI_UDM1W_BASE 0xFF801BC0
+#define SYS_AXI_ADMW_BASE 0xFF801D00
+#define SYS_AXI_ADSW_BASE 0xFF801D40
+#define SYS_AXI_SYXW_BASE 0xFF801FB8
+
+#define RT_AXI_SHX_BASE 0xFF810100
+#define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
+#define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */
+#define RT_AXI_RDS_BASE 0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE 0xFF810200
+#define RT_AXI_STPRO_BASE 0xFF810240
+#define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
+#define RT_AXI_RT_BASE 0xFF810FC0
+#define RT_AXI_SHXW_BASE 0xFF811100
+#define RT_AXI_DBGW_BASE 0xFF811140
+#define RT_AXI_RTX64TO128W_BASE 0xFF811200
+#define RT_AXI_RTW_BASE 0xFF811FC0
+
+#define MP_AXI_ADSP_BASE 0xFF820100
+#define MP_AXI_ASDS0_BASE 0xFF8201C0
+#define MP_AXI_ASDS1_BASE 0xFF820200
+#define MP_AXI_MLP_BASE 0xFF820240
+#define MP_AXI_MMUMP_BASE 0xFF820280
+#define MP_AXI_SPU_BASE 0xFF8202C0
+#define MP_AXI_SPUC_BASE 0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
+#define SYS_AXI256_SYX_BASE 0xFF860140
+#define SYS_AXI256_AXM_BASE 0xFF860140
+#define SYS_AXI256_MPX_BASE 0xFF860180
+#define SYS_AXI256_MXI_BASE 0xFF8601C0
+#define SYS_AXI256_IMP0_BASE 0xFF860580
+#define SYS_AXI256_SY2_BASE 0xFF860FC0
+#define SYS_AXI256_AXI128TO256W_BASE 0xFF861100
+#define SYS_AXI256_AXMW_BASE 0xFF861140
+#define SYS_AXI256_MXIW_BASE 0xFF8611C0
+#define SYS_AXI256_IMP0W_BASE 0xFF861580
+#define SYS_AXI256_SY2W_BASE 0xFF861FC0
+
+#define CCI_AXI_MMUS0_BASE 0xFF880100
+#define CCI_AXI_SYX2_BASE 0xFF880140
+#define CCI_AXI_MMUR_BASE 0xFF880180
+#define CCI_AXI_MMUDS_BASE 0xFF8801C0
+#define CCI_AXI_MMUM_BASE 0xFF880200
+#define CCI_AXI_MXI_BASE 0xFF880240
+#define CCI_AXI_MMUS1_BASE 0xFF880280
+#define CCI_AXI_MMUMP_BASE 0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */
+#define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */
+#define MEDIA_AXI_JPR_BASE 0xFE964100
+#define MEDIA_AXI_JPW_BASE 0xFE966100
+#define MEDIA_AXI_GCU0R_BASE 0xFE964140
+#define MEDIA_AXI_GCU0W_BASE 0xFE966140
+#define MEDIA_AXI_GCU1R_BASE 0xFE964180
+#define MEDIA_AXI_GCU1W_BASE 0xFE966180
+#define MEDIA_AXI_TDMR_BASE 0xFE964500
+#define MEDIA_AXI_TDMW_BASE 0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
+#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
+#define MEDIA_AXI_IMSR_BASE 0xFE964D80
+#define MEDIA_AXI_IMSW_BASE 0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE 0xFE965100
+#define MEDIA_AXI_VSP1W_BASE 0xFE967100
+#define MEDIA_AXI_FDP1R_BASE 0xFE965140
+#define MEDIA_AXI_FDP1W_BASE 0xFE967140
+#define MEDIA_AXI_IMRR_BASE 0xFE965180
+#define MEDIA_AXI_IMRW_BASE 0xFE967180
+#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
+#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
+#define MEDIA_AXI_VPC0R_BASE 0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
+
+#if defined (CONFIG_R8A7792)
+#define MEDIA_AXI_VCTU0R_BASE 0xFE964500 /* R8A7792 */
+#define MEDIA_AXI_VCTU0W_BASE 0xFE966500
+#define MEDIA_AXI_VDCTU0R_BASE 0xFE964540
+#define MEDIA_AXI_VDCTU0W_BASE 0xFE966540
+#define MEDIA_AXI_VDCTU1R_BASE 0xFE964580
+#define MEDIA_AXI_VDCTU1W_BASE 0xFE966580
+#define MEDIA_AXI_VIN0W_BASE 0xFE967580
+#define MEDIA_AXI_VIN1W_BASE 0xFE966D80
+#define MEDIA_AXI_RDRW_BASE 0xFE9675C0
+#define MEDIA_AXI_IMS01R_BASE 0xFE965500
+#define MEDIA_AXI_IMS01W_BASE 0xFE967500
+#define MEDIA_AXI_IMS23R_BASE 0xFE965540 /* FIXME */
+#define MEDIA_AXI_IMS23W_BASE 0xFE967540
+#define MEDIA_AXI_IMS45R_BASE 0xFE964D00
+#define MEDIA_AXI_IMS45W_BASE 0xFE966D00
+#define MEDIA_AXI_ROTCE4R_BASE 0xFE965100
+#define MEDIA_AXI_ROTCE4W_BASE 0xFE967100
+#define MEDIA_AXI_ROTVLC4R_BASE 0xFE965140
+#define MEDIA_AXI_ROTVLC4W_BASE 0xFE965140
+#define MEDIA_AXI_VSPD0R_BASE 0xFE964900
+#define MEDIA_AXI_VSPD0W_BASE 0xFE966900
+#define MEDIA_AXI_VSPD1R_BASE 0xFE964940
+#define MEDIA_AXI_VSPD1W_BASE 0xFE966940
+#define MEDIA_AXI_DU0R_BASE 0xFE964980
+#define MEDIA_AXI_DU0W_BASE 0xFE966980
+#define MEDIA_AXI_VSP0R_BASE 0xFE9649C0
+#define MEDIA_AXI_VSP0W_BASE 0xFE9669C0
+#define MEDIA_AXI_ROTCE0R_BASE 0xFE965900
+#define MEDIA_AXI_ROTCE0W_BASE 0xFE967900
+#define MEDIA_AXI_ROTVLC0R_BASE 0xFE965940
+#define MEDIA_AXI_ROTVLC0W_BASE 0xFE967940
+#define MEDIA_AXI_ROTCE1R_BASE 0xFE965980
+#define MEDIA_AXI_ROTCE1W_BASE 0xFE967980
+#define MEDIA_AXI_ROTVLC1R_BASE 0xFE9659C0
+#define MEDIA_AXI_ROTVLC1W_BASE 0xFE9679C0
+#define MEDIA_AXI_ROTCE2R_BASE 0xFE965D00
+#define MEDIA_AXI_ROTCE2W_BASE 0xFE967D00
+#define MEDIA_AXI_ROTVLC2R_BASE 0xFE965D40
+#define MEDIA_AXI_ROTVLC2W_BASE 0xFE967D40
+#define MEDIA_AXI_ROTCE3R_BASE 0xFE965D80
+#define MEDIA_AXI_ROTCE3W_BASE 0xFE967D80
+#define MEDIA_AXI_ROTVLC3R_BASE 0xFE965DC0
+#define MEDIA_AXI_ROTVLC3W_BASE 0xFE967DC0
+#else /* R8A7792 */
+#define MEDIA_AXI_VIN0W_BASE 0xFE966900
+#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
+#define MEDIA_AXI_DU0R_BASE 0xFE965580
+#define MEDIA_AXI_DU0W_BASE 0xFE967580
+#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
+#endif /* R8A7792 */
+
+
+#define SYS_AXI_AVBDMSCR 0xFF802000
+#define SYS_AXI_SYX2DMSCR 0xFF802004
+#define SYS_AXI_AX2MDMSCR 0xFF802004
+#define SYS_AXI_CC50DMSCR 0xFF802008
+#define SYS_AXI_CC51DMSCR 0xFF80200C
+#define SYS_AXI_CCIDMSCR 0xFF802010
+#define SYS_AXI_CSDMSCR 0xFF802014
+#define SYS_AXI_DDMDMSCR 0xFF802018
+#define SYS_AXI_ETHDMSCR 0xFF80201C
+#define SYS_AXI_G2DDMSCR 0xFF802020
+#define SYS_AXI_IMP0DMSCR 0xFF802024
+#define SYS_AXI_IMP1DMSCR 0xFF802028
+#define SYS_AXI_LBSDMSCR 0xFF80202C
+#define SYS_AXI_MMUDSDMSCR 0xFF802030
+#define SYS_AXI_MMUMXDMSCR 0xFF802034
+#define SYS_AXI_MMURDDMSCR 0xFF802038
+#define SYS_AXI_MMUS0DMSCR 0xFF80203C
+#define SYS_AXI_MMUS1DMSCR 0xFF802040
+#define SYS_AXI_MPXDMSCR 0xFF802044
+#define SYS_AXI_MTSB0DMSCR 0xFF802048
+#define SYS_AXI_MTSB1DMSCR 0xFF80204C
+#define SYS_AXI_PCIDMSCR 0xFF802050
+#define SYS_AXI_RTXDMSCR 0xFF802054
+#define SYS_AXI_SAT0DMSCR 0xFF802058
+#define SYS_AXI_SAT1DMSCR 0xFF80205C
+#define SYS_AXI_SDM0DMSCR 0xFF802060
+#define SYS_AXI_SDM1DMSCR 0xFF802064
+#define SYS_AXI_SDS0DMSCR 0xFF802068
+#define SYS_AXI_SDS1DMSCR 0xFF80206C
+#define SYS_AXI_ETRABDMSCR 0xFF802070
+#define SYS_AXI_ETRKFDMSCR 0xFF802074
+#define SYS_AXI_UDM0DMSCR 0xFF802078
+#define SYS_AXI_UDM1DMSCR 0xFF80207C
+#define SYS_AXI_USB20DMSCR 0xFF802080
+#define SYS_AXI_USB21DMSCR 0xFF802084
+#define SYS_AXI_USB22DMSCR 0xFF802088
+#define SYS_AXI_USB30DMSCR 0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
+#define SYS_AXI_AVBSLVDMSCR 0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
+#define SYS_AXI_AX2SLVDMSCR 0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR 0xFF802110
+#define SYS_AXI_GICSLVDMSCR 0xFF802114
+#define SYS_AXI_IMPSLVDMSCR 0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
+#define SYS_AXI_LBSSLVDMSCR 0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
+#define SYS_AXI_MPXSLVDMSCR 0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR 0xFF802140
+#define SYS_AXI_PCISLVDMSCR 0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR 0xFF802150
+#define SYS_AXI_SAPC1SLVDMSCR 0xFF802154
+#define SYS_AXI_SAPC2SLVDMSCR 0xFF802158
+#define SYS_AXI_SAPC3SLVDMSCR 0xFF80215C
+#define SYS_AXI_SAPC65SLVDMSCR 0xFF802160
+#define SYS_AXI_SAPC8SLVDMSCR 0xFF802164
+#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR 0xFF802180
+#define SYS_AXI_SGXSLV1SLVDMSCR 0xFF802184
+#define SYS_AXI_STBSLVDMSCR 0xFF802188
+#define SYS_AXI_STMSLVDMSCR 0xFF80218C
+#define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR 0xFF802190
+#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
+#define SYS_AXI_UTLBDSSLVDMSCR 0xFF8021B0
+#define SYS_AXI_UTLBS0SLVDMSCR 0xFF8021B4
+#define SYS_AXI_UTLBS1SLVDMSCR 0xFF8021B8
+#define SYS_AXI_ROT0DMSCR 0xFF802320
+#define SYS_AXI_ROT1DMSCR 0xFF802324
+#define SYS_AXI_ROT2DMSCR 0xFF802328
+#define SYS_AXI_ROT3DMSCR 0xFF80232C
+#define SYS_AXI_ROT4DMSCR 0xFF802330
+#define SYS_AXI_IMUX3SLVDMSCR 0xFF802334
+#define SYS_AXI_STBR0SLVDMSCR 0xFF803200
+#define SYS_AXI_STBR0PSLVDMSCR 0xFF803204
+#define SYS_AXI_STBR0XSLVDMSCR 0xFF803208
+#define SYS_AXI_STBR1SLVDMSCR 0xFF803210
+#define SYS_AXI_STBR1PSLVDMSCR 0xFF803214
+#define SYS_AXI_STBR1XSLVDMSCR 0xFF803218
+#define SYS_AXI_STBR2SLVDMSCR 0xFF803220
+#define SYS_AXI_STBR2PSLVDMSCR 0xFF803224
+#define SYS_AXI_STBR2XSLVDMSCR 0xFF803228
+#define SYS_AXI_STBR3SLVDMSCR 0xFF803230
+#define SYS_AXI_STBR3PSLVDMSCR 0xFF803234
+#define SYS_AXI_STBR3XSLVDMSCR 0xFF803238
+#define SYS_AXI_STBR4SLVDMSCR 0xFF803240
+#define SYS_AXI_STBR4PSLVDMSCR 0xFF803244
+#define SYS_AXI_STBR4XSLVDMSCR 0xFF803248
+#define SYS_AXI_ADM_DMSCR 0xFF803260
+#define SYS_AXI_ADS_DMSCR 0xFF803264
+
+#define RT_AXI_CBMDMSCR 0xFF812000
+#define RT_AXI_DBDMSCR 0xFF812004
+#define RT_AXI_RDMDMSCR 0xFF812008
+#define RT_AXI_RDSDMSCR 0xFF81200C
+#define RT_AXI_STRDMSCR 0xFF812010
+#define RT_AXI_SY2RTDMSCR 0xFF812014
+#define RT_AXI_CBSSLVDMSCR 0xFF812100
+#define RT_AXI_DBSSLVDMSCR 0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
+
+#define MP_AXI_ADSPDMSCR 0xFF822000
+#define MP_AXI_ASDM0DMSCR 0xFF822004
+#define MP_AXI_ASDM1DMSCR 0xFF822008
+#define MP_AXI_ASDS0DMSCR 0xFF82200C
+#define MP_AXI_ASDS1DMSCR 0xFF822010
+#define MP_AXI_MLPDMSCR 0xFF822014
+#define MP_AXI_MMUMPDMSCR 0xFF822018
+#define MP_AXI_SPUDMSCR 0xFF82201C
+#define MP_AXI_SPUCDMSCR 0xFF822020
+#define MP_AXI_SY2MPDMSCR 0xFF822024
+#define MP_AXI_ADSPSLVDMSCR 0xFF822100
+#define MP_AXI_MLMSLVDMSCR 0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
+#define MP_AXI_SPUSLVDMSCR 0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR 0xFF842000
+#define ADM_AXI_ASDM1DMSCR 0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
+
+#define DM_AXI_DMAXICONF 0xFF850000
+#define DM_AXI_DMAPBCONF 0xFF850004
+#define DM_AXI_DMADMCONF 0xFF850020
+#define DM_AXI_DMSDM0CONF 0xFF850024
+#define DM_AXI_DMSDM1CONF 0xFF850028
+#define DM_AXI_DMQSPAPSLVCONF 0xFF850030
+#define DM_AXI_RAPD4SLVCONF 0xFF850034
+#define DM_AXI_SAPD4SLVCONF 0xFF85003C
+#define DM_AXI_SAPD5SLVCONF 0xFF850040
+#define DM_AXI_SAPD6SLVCONF 0xFF850044
+#define DM_AXI_SAPD65DSLVCONF 0xFF850048
+#define DM_AXI_SDAP0SLVCONF 0xFF85004C
+#define DM_AXI_MAPD2SLVCONF 0xFF850050
+#define DM_AXI_MAPD3SLVCONF 0xFF850054
+#define DM_AXI_DMXXDEFAULTSLAVESLVCONF 0xFF850058
+#define DM_AXI_DMADMRQOSCONF 0xFF850100
+#define DM_AXI_DMADMRQOSCTSET0 0xFF850104
+#define DM_AXI_DMADMRQOSREQCTR 0xFF850114
+#define DM_AXI_DMADMRQOSQON 0xFF850124
+#define DM_AXI_DMADMRQOSIN 0xFF850128
+#define DM_AXI_DMADMRQOSSTAT 0xFF85012C
+#define DM_AXI_DMSDM0RQOSCONF 0xFF850140
+#define DM_AXI_DMSDM0RQOSCTSET0 0xFF850144
+#define DM_AXI_DMSDM0RQOSREQCTR 0xFF850154
+#define DM_AXI_DMSDM0RQOSQON 0xFF850164
+#define DM_AXI_DMSDM0RQOSIN 0xFF850168
+#define DM_AXI_DMSDM0RQOSSTAT 0xFF85016C
+#define DM_AXI_DMSDM1RQOSCONF 0xFF850180
+#define DM_AXI_DMSDM1RQOSCTSET0 0xFF850184
+#define DM_AXI_DMSDM1RQOSREQCTR 0xFF850194
+#define DM_AXI_DMSDM1RQOSQON 0xFF8501A4
+#define DM_AXI_DMSDM1RQOSIN 0xFF8501A8
+#define DM_AXI_DMSDM1RQOSSTAT 0xFF8501AC
+#define DM_AXI_DMRQOSCTSET1 0xFF850FC0
+#define DM_AXI_DMRQOSCTSET2 0xFF850FC4
+#define DM_AXI_DMRQOSCTSET3 0xFF850FC8
+#define DM_AXI_DMRQOSTHRES0 0xFF850FCC
+#define DM_AXI_DMRQOSTHRES1 0xFF850FD0
+#define DM_AXI_DMRQOSTHRES2 0xFF850FD4
+#define DM_AXI_DMADMWQOSCONF 0xFF851100
+#define DM_AXI_DMADMWQOSCTSET0 0xFF851104
+#define DM_AXI_DMADMWQOSREQCTR 0xFF851114
+#define DM_AXI_DMADMWQOSQON 0xFF851124
+#define DM_AXI_DMADMWQOSIN 0xFF851128
+#define DM_AXI_DMADMWQOSSTAT 0xFF85112C
+#define DM_AXI_DMSDM0WQOSCONF 0xFF851140
+#define DM_AXI_DMSDM0WQOSCTSET0 0xFF851144
+#define DM_AXI_DMSDM0WQOSREQCTR 0xFF851154
+#define DM_AXI_DMSDM0WQOSQON 0xFF851164
+#define DM_AXI_DMSDM0WQOSIN 0xFF851168
+#define DM_AXI_DMSDM0WQOSSTAT 0xFF85116C
+#define DM_AXI_DMSDM1WQOSCONF 0xFF851180
+#define DM_AXI_DMSDM1WQOSCTSET0 0xFF851184
+#define DM_AXI_DMSDM1WQOSREQCTR 0xFF851194
+#define DM_AXI_DMSDM1WQOSQON 0xFF8511A4
+#define DM_AXI_DMSDM1WQOSIN 0xFF8511A8
+#define DM_AXI_DMSDM1WQOSSTAT 0xFF8511AC
+#define DM_AXI_DMWQOSCTSET1 0xFF851FC0
+#define DM_AXI_DMWQOSCTSET2 0xFF851FC4
+#define DM_AXI_DMWQOSCTSET3 0xFF851FC8
+#define DM_AXI_DMWQOSTHRES0 0xFF851FCC
+#define DM_AXI_DMWQOSTHRES1 0xFF851FD0
+#define DM_AXI_DMWQOSTHRES2 0xFF851FD4
+
+#define DM_AXI_RDMDMSCR 0xFF852000
+#define DM_AXI_SDM0DMSCR 0xFF852004
+#define DM_AXI_SDM1DMSCR 0xFF852008
+#if defined(CONFIG_R8A7792)
+#define DM_AXI_DMQSPAPSLVDMSCR 0xFF852104
+#define DM_AXI_RAPD4SLVDMSCR 0xFF852108
+#define DM_AXI_SAPD4SLVDMSCR 0xFF852110
+#define DM_AXI_SAPD5SLVDMSCR 0xFF852114
+#define DM_AXI_SAPD6SLVDMSCR 0xFF852118
+#define DM_AXI_SAPD65DSLVDMSCR 0xFF85211C
+#define DM_AXI_SDAP0SLVDMSCR 0xFF852120
+#define DM_AXI_MAPD2SLVDMSCR 0xFF852124
+#define DM_AXI_MAPD3SLVDMSCR 0xFF852128
+#define DM_AXI_DMXXDEFAULTSLAVESLVDMSCR 0xFF85212C
+#define DM_AXI_DMXREGDMSENN 0xFF852200
+#else
+#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
+#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR 0xFF852110
+#define DM_AXI_SAP4SLVDMSCR 0xFF852114
+#define DM_AXI_SAP5SLVDMSCR 0xFF852118
+#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR 0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
+#endif
+
+#define SYS_AXI256_SYXDMSCR 0xFF862000
+#define SYS_AXI256_MPXDMSCR 0xFF862004
+#define SYS_AXI256_MXIDMSCR 0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
+
+#define MXT_SYXDMSCR 0xFF872000
+#if defined(CONFIG_R8A7792)
+#define MXT_IMRSLVDMSCR 0xFF872110
+#define MXT_VINSLVDMSCR 0xFF872114
+#define MXT_VSP1SLVDMSCR 0xFF87211C
+#define MXT_VSPD0SLVDMSCR 0xFF872120
+#define MXT_VSPD1SLVDMSCR 0xFF872124
+#define MXT_MAP1SLVDMSCR 0xFF872128
+#define MXT_MAP2SLVDMSCR 0xFF87212C
+#define MXT_MAP2BSLVDMSCR 0xFF872134
+#else /* R8A7792 */
+#define MXT_CMM0SLVDMSCR 0xFF872100
+#define MXT_CMM1SLVDMSCR 0xFF872104
+#define MXT_CMM2SLVDMSCR 0xFF872108
+#define MXT_FDPSLVDMSCR 0xFF87210C
+#define MXT_IMRSLVDMSCR 0xFF872110
+#define MXT_VINSLVDMSCR 0xFF872114
+#define MXT_VPC0SLVDMSCR 0xFF872118
+#define MXT_VPC1SLVDMSCR 0xFF87211C
+#define MXT_VSP0SLVDMSCR 0xFF872120
+#define MXT_VSP1SLVDMSCR 0xFF872124
+#define MXT_VSPD0SLVDMSCR 0xFF872128
+#define MXT_VSPD1SLVDMSCR 0xFF87212C
+#define MXT_MAP1SLVDMSCR 0xFF872130
+#define MXT_MAP2SLVDMSCR 0xFF872134
+#endif /* R8A7792 */
+
+/* DMS Register (MXI) */
+#if defined(CONFIG_R8A7792)
+#define MXI_JPURDMSCR 0xFE964200
+#define MXI_JPUWDMSCR 0xFE966200
+#define MXI_VCTU0RDMSCR 0xFE964600
+#define MXI_VCTU0WDMSCR 0xFE966600
+#define MXI_VDCTU0RDMSCR 0xFE964604
+#define MXI_VDCTU0WDMSCR 0xFE966604
+#define MXI_VDCTU1RDMSCR 0xFE964608
+#define MXI_VDCTU1WDMSCR 0xFE966608
+#define MXI_VIN0WDMSCR 0xFE967608
+#define MXI_VIN1WDMSCR 0xFE966E08
+#define MXI_RDRWDMSCR 0xFE96760C
+#define MXI_IMS01RDMSCR 0xFE965600
+#define MXI_IMS01WDMSCR 0xFE967600
+#define MXI_IMS23RDMSCR 0xFE965604
+#define MXI_IMS23WDMSCR 0xFE967604
+#define MXI_IMS45RDMSCR 0xFE964E00
+#define MXI_IMS45WDMSCR 0xFE966E00
+#define MXI_IMRRDMSCR 0xFE964E04
+#define MXI_IMRWDMSCR 0xFE966E04
+#define MXI_ROTCE4RDMSCR 0xFE965200
+#define MXI_ROTCE4WDMSCR 0xFE967200
+#define MXI_ROTVLC4RDMSCR 0xFE965204
+#define MXI_ROTVLC4WDMSCR 0xFE967204
+#define MXI_VSPD0RDMSCR 0xFE964A00
+#define MXI_VSPD0WDMSCR 0xFE966A00
+#define MXI_VSPD1RDMSCR 0xFE964A04
+#define MXI_VSPD1WDMSCR 0xFE966A04
+#define MXI_DU0RDMSCR 0xFE964A08
+#define MXI_DU0WDMSCR 0xFE966A08
+#define MXI_VSP0RDMSCR 0xFE964A0C
+#define MXI_VSP0WDMSCR 0xFE966A0C
+#define MXI_ROTCE0RDMSCR 0xFE965A00
+#define MXI_ROTCE0WDMSCR 0xFE967A00
+#define MXI_ROTVLC0RDMSCR 0xFE965A04
+#define MXI_ROTVLC0WDMSCR 0xFE967A04
+#define MXI_ROTCE1RDMSCR 0xFE965A08
+#define MXI_ROTCE1WDMSCR 0xFE967A08
+#define MXI_ROTVLC1RDMSCR 0xFE965A0C
+#define MXI_ROTVLC1WDMSCR 0xFE967A0C
+#define MXI_ROTCE2RDMSCR 0xFE965E00
+#define MXI_ROTCE2WDMSCR 0xFE967E00
+#define MXI_ROTVLC2RDMSCR 0xFE965E04
+#define MXI_ROTVLC2WDMSCR 0xFE967E04
+#define MXI_ROTCE3RDMSCR 0xFE965E08
+#define MXI_ROTCE3WDMSCR 0xFE967E08
+#define MXI_ROTVLC3RDMSCR 0xFE965E0C
+#define MXI_ROTVLC3WDMSCR 0xFE967E0C
+#endif /* R8A7792 */
+
+#define CCI_AXI_MMUS0DMSCR 0xFF882000
+#define CCI_AXI_SYX2DMSCR 0xFF882004
+#define CCI_AXI_MMURDMSCR 0xFF882008
+#define CCI_AXI_MMUDSDMSCR 0xFF88200C
+#define CCI_AXI_MMUMDMSCR 0xFF882010
+#define CCI_AXI_MXIDMSCR 0xFF882014
+#define CCI_AXI_MMUS1DMSCR 0xFF882018
+#define CCI_AXI_MMUMPDMSCR 0xFF88201C
+#define CCI_AXI_DVMDMSCR 0xFF882020
+#define CCI_AXI_CCISLVDMSCR 0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR 0xFF880400
+#define CCI_AXI_IPMMURDVMCR 0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
+#define CCI_AXI_AX2ADDRMASK 0xFF88041C
+
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct rcar_rwdt {
+ u32 rwtcnt; /* 0x00 */
+ u32 rwtcsra; /* 0x04 */
+ u16 rwtcsrb; /* 0x08 */
+};
+
+/* SWDT */
+struct rcar_swdt {
+ u32 swtcnt; /* 0x00 */
+ u32 swtcsra; /* 0x04 */
+ u16 swtcsrb; /* 0x08 */
+};
+
+/* LBSC */
+struct rcar_lbsc {
+ u32 cs0ctrl;
+ u32 cs1ctrl;
+ u32 ecs0ctrl;
+ u32 ecs1ctrl;
+ u32 ecs2ctrl;
+ u32 ecs3ctrl;
+ u32 ecs4ctrl;
+ u32 ecs5ctrl;
+ u32 dummy0[4]; /* 0x20 .. 0x2C */
+ u32 cswcr0;
+ u32 cswcr1;
+ u32 ecswcr0;
+ u32 ecswcr1;
+ u32 ecswcr2;
+ u32 ecswcr3;
+ u32 ecswcr4;
+ u32 ecswcr5;
+ u32 exdmawcr0;
+ u32 exdmawcr1;
+ u32 exdmawcr2;
+ u32 dummy1[9]; /* 0x5C .. 0x7C */
+ u32 cspwcr0;
+ u32 cspwcr1;
+ u32 ecspwcr0;
+ u32 ecspwcr1;
+ u32 ecspwcr2;
+ u32 ecspwcr3;
+ u32 ecspwcr4;
+ u32 ecspwcr5;
+ u32 exwtsync;
+ u32 dummy2[3]; /* 0xA4 .. 0xAC */
+ u32 cs0bstctl;
+ u32 cs0btph;
+ u32 dummy3[2]; /* 0xB8 .. 0xBC */
+ u32 cs1gdst;
+ u32 ecs0gdst;
+ u32 ecs1gdst;
+ u32 ecs2gdst;
+ u32 ecs3gdst;
+ u32 ecs4gdst;
+ u32 ecs5gdst;
+ u32 dummy4[5]; /* 0xDC .. 0xEC */
+ u32 exdmaset0;
+ u32 exdmaset1;
+ u32 exdmaset2;
+ u32 dummy5[5]; /* 0xFC .. 0x10C */
+ u32 exdmcr0;
+ u32 exdmcr1;
+ u32 exdmcr2;
+ u32 dummy6[5]; /* 0x11C .. 0x12C */
+ u32 bcintsr;
+ u32 bcintcr;
+ u32 bcintmr;
+ u32 dummy7; /* 0x13C */
+ u32 exbatlv;
+ u32 exwtsts;
+ u32 dummy8[14]; /* 0x148 .. 0x17C */
+ u32 atacsctrl;
+ u32 dummy9[15]; /* 0x184 .. 0x1BC */
+ u32 exbct;
+ u32 extct;
+};
+
+/* DBSC3 */
+struct rcar_dbsc3 {
+ u32 dummy0[3]; /* 0x00 .. 0x08 */
+ u32 dbstate1;
+ u32 dbacen;
+ u32 dbrfen;
+ u32 dbcmd;
+ u32 dbwait;
+ u32 dbkind;
+ u32 dbconf0;
+ u32 dummy1[2]; /* 0x28 .. 0x2C */
+ u32 dbphytype;
+ u32 dummy2[3]; /* 0x34 .. 0x3C */
+ u32 dbtr0;
+ u32 dbtr1;
+ u32 dbtr2;
+ u32 dummy3; /* 0x4C */
+ u32 dbtr3;
+ u32 dbtr4;
+ u32 dbtr5;
+ u32 dbtr6;
+ u32 dbtr7;
+ u32 dbtr8;
+ u32 dbtr9;
+ u32 dbtr10;
+ u32 dbtr11;
+ u32 dbtr12;
+ u32 dbtr13;
+ u32 dbtr14;
+ u32 dbtr15;
+ u32 dbtr16;
+ u32 dbtr17;
+ u32 dbtr18;
+ u32 dbtr19;
+ u32 dummy4[7]; /* 0x94 .. 0xAC */
+ u32 dbbl;
+ u32 dummy5[3]; /* 0xB4 .. 0xBC */
+ u32 dbadj0;
+ u32 dummy6; /* 0xC4 */
+ u32 dbadj2;
+ u32 dummy7[5]; /* 0xCC .. 0xDC */
+ u32 dbrfcnf0;
+ u32 dbrfcnf1;
+ u32 dbrfcnf2;
+ u32 dummy8[2]; /* 0xEC .. 0xF0 */
+ u32 dbcalcnf;
+ u32 dbcaltr;
+ u32 dummy9; /* 0xFC */
+ u32 dbrnk0;
+ u32 dummy10[31]; /* 0x104 .. 0x17C */
+ u32 dbpdncnf;
+ u32 dummy11[47]; /* 0x184 ..0x23C */
+ u32 dbdfistat;
+ u32 dbdficnt;
+ u32 dummy12[14]; /* 0x248 .. 0x27C */
+ u32 dbpdlck;
+ u32 dummy13[3]; /* 0x284 .. 0x28C */
+ u32 dbpdrga;
+ u32 dummy14[3]; /* 0x294 .. 0x29C */
+ u32 dbpdrgd;
+ u32 dummy15[24]; /* 0x2A4 .. 0x300 */
+ u32 dbbs0cnt1;
+ u32 dummy16[30]; /* 0x308 .. 0x37C */
+ u32 dbwt0cnf0;
+ u32 dbwt0cnf1;
+ u32 dbwt0cnf2;
+ u32 dbwt0cnf3;
+ u32 dbwt0cnf4;
+ u32 dummy17[27]; /* 0x394 .. 0x3FC */
+ u32 dbeccmode;
+ u32 dummy18[3]; /* 0x404 .. 0x40C */
+ u32 dbeccarea0;
+ u32 dbeccarea1;
+ u32 dbeccarea2;
+ u32 dbeccarea3;
+ u32 dummy19[4]; /* 0x420 .. 0x42C */
+ u32 dbeccintenable;
+ u32 dbeccintdetect;
+ u32 dummy20[22]; /* 0x438 .. 0x48C */
+ u32 dbeccmodulcnt;
+ u32 dummy21[27]; /* 0x494 .. 0x4FC */
+ u32 dbschecnt0;
+ u32 dummy22[63]; /* 0x504 .. 0x5FC */
+ u32 dbreradr0;
+ u32 dbreblane0;
+ u32 dbrerid0;
+ u32 dbrerinfo0;
+ u32 dbureradr0;
+ u32 dbureblane0;
+ u32 dburerid0;
+ u32 dburerinfo0;
+ u32 dbreradr1;
+ u32 dbreblane1;
+ u32 dbrerid1;
+ u32 dbrerinfo1;
+ u32 dbureradr1;
+ u32 dbureblane1;
+ u32 dburerid1;
+ u32 dburerinfo1;
+ u32 dbreradr2;
+ u32 dbreblane2;
+ u32 dbrerid2;
+ u32 dbrerinfo2;
+ u32 dbureradr2;
+ u32 dbureblane2;
+ u32 dburerid2;
+ u32 dburerinfo2;
+ u32 dbreradr3;
+ u32 dbreblane3;
+ u32 dbrerid3;
+ u32 dbrerinfo3;
+ u32 dbureradr3;
+ u32 dbureblane3;
+ u32 dburerid3;
+ u32 dburerinfo3;
+ u32 dummy23[160]; /* 0x680 .. 0x8FC */
+ u32 dbpccr;
+ u32 dbpeier;
+ u32 dbpeisr;
+ u32 dummy24;
+ u32 dbwdpesr0;
+ u32 dbwspesr0;
+ u32 dbpwear0;
+ u32 dbpweid0;
+ u32 dbpweinfo0;
+ u32 dummy25[3]; /* 0x924 .. 0x92C */
+ u32 dbwdpesr1;
+ u32 dbwspesr1;
+ u32 dbpwear1;
+ u32 dbpweid1;
+ u32 dbpweinfo1;
+ u32 dummy26[3]; /* 0x944 .. 0x94C */
+ u32 dbwdpesr2;
+ u32 dbwspesr2;
+ u32 dbpwear2;
+ u32 dbpweid2;
+ u32 dbpweinfo2;
+ u32 dummy27[3]; /* 0x964 .. 0x96C */
+ u32 dbwdpesr3;
+ u32 dbwspesr3;
+ u32 dbpwear3;
+ u32 dbpweid3;
+ u32 dbpweinfo3;
+};
+
+/* GPIO */
+struct rcar_gpio {
+ u32 iointsel;
+ u32 inoutsel;
+ u32 outdt;
+ u32 indt;
+ u32 intdt;
+ u32 intclr;
+ u32 intmsk;
+ u32 posneg;
+ u32 edglevel;
+ u32 filonoff;
+ u32 intmsks;
+ u32 mskclrs;
+ u32 outdtsel;
+ u32 outdth;
+ u32 outdtl;
+ u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct rcar_s3c {
+ u32 s3cexcladdmsk;
+ u32 s3cexclidmsk;
+ u32 s3cadsplcr;
+ u32 s3cmaar;
+ u32 s3carcr11;
+ u32 s3crorr;
+ u32 s3cworr;
+ u32 s3carcr22;
+ u32 dummy1[2]; /* 0x20 .. 0x24 */
+ u32 s3cmctr;
+ u32 dummy2; /* 0x2C */
+ u32 cconf0;
+ u32 cconf1;
+ u32 cconf2;
+ u32 cconf3;
+};
+
+struct rcar_s3c_qos {
+ u32 s3cqos0;
+ u32 s3cqos1;
+ u32 s3cqos2;
+ u32 s3cqos3;
+ u32 s3cqos4;
+ u32 s3cqos5;
+ u32 s3cqos6;
+ u32 s3cqos7;
+ u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct rcar_dbsc3_qos {
+ u32 dblgcnt;
+ u32 dbtmval0;
+ u32 dbtmval1;
+ u32 dbtmval2;
+ u32 dbtmval3;
+ u32 dbrqctr;
+ u32 dbthres0;
+ u32 dbthres1;
+ u32 dbthres2;
+ u32 dummy0; /* 0x24 */
+ u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct rcar_mxi {
+ u32 mxsaar0;
+ u32 mxsaar1;
+ u32 dummy0[7]; /* 0x08 .. 0x20 */
+ u32 mxaxiracr; /* R8a7790 only */
+ u32 mxs3cracr;
+ u32 dummy1[2]; /* 0x2C .. 0x30 */
+ u32 mxaxiwacr; /* R8a7790 only */
+ u32 mxs3cwacr;
+ u32 dummy2; /* 0x3C */
+ u32 mxrtcr;
+ u32 mxwtcr;
+ u32 mxaxirtcr; /* R8a7792 only */
+ u32 mxaxiwtcr;
+ u32 mxs3crtcr;
+ u32 mxs3cwtcr;
+};
+
+struct rcar_mxi_qos {
+ u32 vspdu0;
+ u32 vspdu1;
+ u32 du0;
+ u32 du1;
+};
+
+/* AXI(QoS) */
+struct rcar_axi_qos {
+ u32 qosconf;
+ u32 qosctset0;
+ u32 qosctset1;
+ u32 qosctset2;
+ u32 qosctset3;
+ u32 qosreqctr;
+ u32 qosthres0;
+ u32 qosthres1;
+ u32 qosthres2;
+ u32 qosqon;
+ u32 qosin;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_RCAR_BASE_H */
diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
new file mode 100644
index 0000000..5e2e9ec
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ./arch/arm/mach-renesas/include/mach/rcar-gen3-base.h
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
+#define __ASM_ARCH_RCAR_GEN3_BASE_H
+
+/*
+ * R-Car (R8A7750) I/O Addresses
+ */
+#define RWDT_BASE 0xE6020000
+#define SWDT_BASE 0xE6030000
+#define LBSC_BASE 0xEE220200
+#define TMU_BASE 0xE61E0000
+#define GPIO5_BASE 0xE6055000
+
+/* SCIF */
+#define SCIF0_BASE 0xE6E60000
+#define SCIF1_BASE 0xE6E68000
+#define SCIF2_BASE 0xE6E88000
+#define SCIF3_BASE 0xE6C50000
+#define SCIF4_BASE 0xE6C40000
+#define SCIF5_BASE 0xE6F30000
+
+/* Module stop status register */
+#define MSTPSR0 0xE6150030
+#define MSTPSR1 0xE6150038
+#define MSTPSR2 0xE6150040
+#define MSTPSR3 0xE6150048
+#define MSTPSR4 0xE615004C
+#define MSTPSR5 0xE615003C
+#define MSTPSR6 0xE61501C0
+#define MSTPSR7 0xE61501C4
+#define MSTPSR8 0xE61509A0
+#define MSTPSR9 0xE61509A4
+#define MSTPSR10 0xE61509A8
+#define MSTPSR11 0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0 0xE6150110
+#define RMSTPCR1 0xE6150114
+#define RMSTPCR2 0xE6150118
+#define RMSTPCR3 0xE615011C
+#define RMSTPCR4 0xE6150120
+#define RMSTPCR5 0xE6150124
+#define RMSTPCR6 0xE6150128
+#define RMSTPCR7 0xE615012C
+#define RMSTPCR8 0xE6150980
+#define RMSTPCR9 0xE6150984
+#define RMSTPCR10 0xE6150988
+#define RMSTPCR11 0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0 0xE6150130
+#define SMSTPCR1 0xE6150134
+#define SMSTPCR2 0xE6150138
+#define SMSTPCR3 0xE615013C
+#define SMSTPCR4 0xE6150140
+#define SMSTPCR5 0xE6150144
+#define SMSTPCR6 0xE6150148
+#define SMSTPCR7 0xE615014C
+#define SMSTPCR8 0xE6150990
+#define SMSTPCR9 0xE6150994
+#define SMSTPCR10 0xE6150998
+#define SMSTPCR11 0xE615099C
+
+/* PFC */
+#define PFC_PUEN5 0xE6060414
+#define PUEN_SSI_SDATA4 BIT(17)
+#define PFC_PUEN6 0xE6060418
+#define PUEN_USB1_OVC (1 << 2)
+#define PUEN_USB1_PWEN (1 << 1)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <linux/bitops.h>
+
+/* RWDT */
+struct rcar_rwdt {
+ u32 rwtcnt;
+ u32 rwtcsra;
+ u32 rwtcsrb;
+};
+
+/* SWDT */
+struct rcar_swdt {
+ u32 swtcnt;
+ u32 swtcsra;
+ u32 swtcsrb;
+};
+#endif
+
+#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */
diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
new file mode 100644
index 0000000..f34473d
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#ifndef __ASM_ARCH_RCAR_GEN4_BASE_H
+#define __ASM_ARCH_RCAR_GEN4_BASE_H
+
+/*
+ * R-Car (R8A779F0) I/O Addresses
+ */
+#define RWDT_BASE 0xE6020000
+#define SWDT_BASE 0xE6030000
+#define TMU_BASE 0xE61E0000
+
+/* SCIF */
+#define SCIF0_BASE 0xE6E60000
+#define SCIF1_BASE 0xE6E68000
+#define SCIF2_BASE 0xE6E88000
+#define SCIF3_BASE 0xE6C50000
+#define SCIF4_BASE 0xE6C40000
+#define SCIF5_BASE 0xE6F30000
+
+/* CPG */
+#define CPGWPR 0xE6150000
+#define CPGWPCR 0xE6150004
+
+/* Reset */
+#define RST_BASE 0xE6160000 /* Domain0 */
+#define RST_SRESCR0 (RST_BASE + 0x18)
+#define RST_SPRES 0x5AA58000
+
+/* Arm Generic Timer */
+#define CNTCR_BASE 0xE6080000
+#define CNTFID0 (CNTCR_BASE + 0x020)
+#define CNTCR_EN BIT(0)
+
+/* GICv3 */
+/* Distributor Registers */
+#define GICD_BASE 0xF1000000
+#define GICR_BASE (GICR_LPI_BASE)
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_LPI_BASE 0xF1060000
+#define GICR_WAKER 0x0014
+#define GICR_PWRR 0x0024
+#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
+#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_SGI_BASE 0xF1070000
+#define GICR_IGROUPR0 0x0080
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <linux/bitops.h>
+
+/* RWDT */
+struct rcar_rwdt {
+ u32 rwtcnt;
+ u32 rwtcsra;
+ u32 rwtcsrb;
+};
+
+/* SWDT */
+struct rcar_swdt {
+ u32 swtcnt;
+ u32 swtcsra;
+ u32 swtcsrb;
+};
+#endif
+
+#endif /* __ASM_ARCH_RCAR_GEN4_BASE_H */
diff --git a/arch/arm/mach-renesas/include/mach/rcar-mstp.h b/arch/arm/mach-renesas/include/mach/rcar-mstp.h
new file mode 100644
index 0000000..7ca362e
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/rcar-mstp.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/include/asm/arch-renesas/rcar-mstp.h
+ *
+ * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_RCAR_MSTP_H
+#define __ASM_ARCH_RCAR_MSTP_H
+
+#define mstp_setbits(type, addr, saddr, set) \
+ out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+ out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setclrbits(type, addr, set, clear) \
+ out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+ mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear) \
+ mstp_clrbits(le32, addr, saddr, clear)
+#define mstp_setclrbits_le32(addr, set, clear) \
+ mstp_setclrbits(le32, addr, set, clear)
+
+#ifndef CFG_SMSTP0_ENA
+#define CFG_SMSTP0_ENA 0x00
+#endif
+#ifndef CFG_SMSTP1_ENA
+#define CFG_SMSTP1_ENA 0x00
+#endif
+#ifndef CFG_SMSTP2_ENA
+#define CFG_SMSTP2_ENA 0x00
+#endif
+#ifndef CFG_SMSTP3_ENA
+#define CFG_SMSTP3_ENA 0x00
+#endif
+#ifndef CFG_SMSTP4_ENA
+#define CFG_SMSTP4_ENA 0x00
+#endif
+#ifndef CFG_SMSTP5_ENA
+#define CFG_SMSTP5_ENA 0x00
+#endif
+#ifndef CFG_SMSTP6_ENA
+#define CFG_SMSTP6_ENA 0x00
+#endif
+#ifndef CFG_SMSTP7_ENA
+#define CFG_SMSTP7_ENA 0x00
+#endif
+#ifndef CFG_SMSTP8_ENA
+#define CFG_SMSTP8_ENA 0x00
+#endif
+#ifndef CFG_SMSTP9_ENA
+#define CFG_SMSTP9_ENA 0x00
+#endif
+#ifndef CFG_SMSTP10_ENA
+#define CFG_SMSTP10_ENA 0x00
+#endif
+#ifndef CFG_SMSTP11_ENA
+#define CFG_SMSTP11_ENA 0x00
+#endif
+
+#ifndef CFG_RMSTP0_ENA
+#define CFG_RMSTP0_ENA 0x00
+#endif
+#ifndef CFG_RMSTP1_ENA
+#define CFG_RMSTP1_ENA 0x00
+#endif
+#ifndef CFG_RMSTP2_ENA
+#define CFG_RMSTP2_ENA 0x00
+#endif
+#ifndef CFG_RMSTP3_ENA
+#define CFG_RMSTP3_ENA 0x00
+#endif
+#ifndef CFG_RMSTP4_ENA
+#define CFG_RMSTP4_ENA 0x00
+#endif
+#ifndef CFG_RMSTP5_ENA
+#define CFG_RMSTP5_ENA 0x00
+#endif
+#ifndef CFG_RMSTP6_ENA
+#define CFG_RMSTP6_ENA 0x00
+#endif
+#ifndef CFG_RMSTP7_ENA
+#define CFG_RMSTP7_ENA 0x00
+#endif
+#ifndef CFG_RMSTP8_ENA
+#define CFG_RMSTP8_ENA 0x00
+#endif
+#ifndef CFG_RMSTP9_ENA
+#define CFG_RMSTP9_ENA 0x00
+#endif
+#ifndef CFG_RMSTP10_ENA
+#define CFG_RMSTP10_ENA 0x00
+#endif
+#ifndef CFG_RMSTP11_ENA
+#define CFG_RMSTP11_ENA 0x00
+#endif
+
+struct mstp_ctl {
+ u32 s_addr;
+ u32 s_dis;
+ u32 s_ena;
+ u32 r_addr;
+ u32 r_dis;
+ u32 r_ena;
+};
+
+#endif /* __ASM_ARCH_RCAR_MSTP_H */
diff --git a/arch/arm/mach-renesas/include/mach/renesas.h b/arch/arm/mach-renesas/include/mach/renesas.h
new file mode 100644
index 0000000..c69c764
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/renesas.h
@@ -0,0 +1,56 @@
+#ifndef __ASM_ARCH_RENESAS_H
+#define __ASM_ARCH_RENESAS_H
+
+#if defined(CONFIG_ARCH_RENESAS)
+#if defined(CONFIG_R8A7790)
+#include <asm/arch/r8a7790.h>
+#elif defined(CONFIG_R8A7791)
+#include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7792)
+#include <asm/arch/r8a7792.h>
+#elif defined(CONFIG_R8A7793)
+#include <asm/arch/r8a7793.h>
+#elif defined(CONFIG_R8A7794)
+#include <asm/arch/r8a7794.h>
+#elif defined(CONFIG_RCAR_GEN3)
+#include <asm/arch/rcar-gen3-base.h>
+#elif defined(CONFIG_RCAR_GEN4)
+#include <asm/arch/rcar-gen4-base.h>
+#elif defined(CONFIG_R7S72100)
+#elif defined(CONFIG_RZG2L)
+#include <asm/arch/rzg2l.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_ARCH_RENESAS */
+
+/* PRR CPU IDs */
+#define RENESAS_CPU_TYPE_R8A7740 0x40
+#define RENESAS_CPU_TYPE_R8A7790 0x45
+#define RENESAS_CPU_TYPE_R8A7791 0x47
+#define RENESAS_CPU_TYPE_R8A7792 0x4A
+#define RENESAS_CPU_TYPE_R8A7793 0x4B
+#define RENESAS_CPU_TYPE_R8A7794 0x4C
+#define RENESAS_CPU_TYPE_R8A7795 0x4F
+#define RENESAS_CPU_TYPE_R8A7796 0x52
+#define RENESAS_CPU_TYPE_R8A77965 0x55
+#define RENESAS_CPU_TYPE_R8A77970 0x54
+#define RENESAS_CPU_TYPE_R8A77980 0x56
+#define RENESAS_CPU_TYPE_R8A77990 0x57
+#define RENESAS_CPU_TYPE_R8A77995 0x58
+#define RENESAS_CPU_TYPE_R8A779A0 0x59
+#define RENESAS_CPU_TYPE_R8A779F0 0x5A
+#define RENESAS_CPU_TYPE_R8A779G0 0x5C
+#define RENESAS_CPU_TYPE_R8A779H0 0x5D
+#define RENESAS_CPU_TYPE_R9A07G044L 0x9A070440
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+const u8 *rzg_get_cpu_name(void);
+u32 renesas_get_cpu_type(void);
+u32 renesas_get_cpu_rev_integer(void);
+u32 renesas_get_cpu_rev_fraction(void);
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_RENESAS_H */
diff --git a/arch/arm/mach-renesas/include/mach/rzg2l.h b/arch/arm/mach-renesas/include/mach/rzg2l.h
new file mode 100644
index 0000000..057df5c
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/rzg2l.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RZ/G2L SoC Family support.
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#ifndef __ASM_ARCH_RZG2L_H
+#define __ASM_ARCH_RZG2L_H
+
+#define GICD_BASE 0x11900000
+#define GICR_BASE 0x11960000
+
+#endif /* __ASM_ARCH_RZG2L_H */
diff --git a/arch/arm/mach-renesas/include/mach/sys_proto.h b/arch/arm/mach-renesas/include/mach/sys_proto.h
new file mode 100644
index 0000000..ec8036a
--- /dev/null
+++ b/arch/arm/mach-renesas/include/mach/sys_proto.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+#endif
diff --git a/arch/arm/mach-renesas/lowlevel_init_ca15.S b/arch/arm/mach-renesas/lowlevel_init_ca15.S
new file mode 100644
index 0000000..a52b761
--- /dev/null
+++ b/arch/arm/mach-renesas/lowlevel_init_ca15.S
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+ * This file is lager low level initialize.
+ *
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <system-constants.h>
+
+ENTRY(lowlevel_init)
+#ifndef CONFIG_SPL_BUILD
+ mrc p15, 0, r4, c0, c0, 5 /* mpidr */
+ orr r4, r4, r4, lsr #6
+ and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
+
+ b do_lowlevel_init
+
+ .pool
+
+/*
+ * CPU ID #1-#3 come here
+ */
+ .align 4
+do_cpu_waiting:
+ ldr r1, =0xe6180000 /* sysc */
+1: ldr r0, [r1, #0x20] /* sbar */
+ tst r0, r0
+ beq 1b
+ bx r0
+
+/*
+ * Only CPU ID #0 comes here
+ */
+ .align 4
+do_lowlevel_init:
+ ldr r2, =0xFF000044 /* PRR */
+ ldr r1, [r2]
+ and r1, r1, #0x7F00
+ lsrs r1, r1, #8
+ cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
+ beq _enable_actlr_smp
+
+ /* surpress wfe if ca15 */
+ tst r4, #4
+ mrceq p15, 0, r0, c1, c0, 1 /* actlr */
+ orreq r0, r0, #(1<<7)
+ mcreq p15, 0, r0, c1, c0, 1
+
+ /* and set l2 latency */
+ mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */
+ and r0, r0, #0xf00
+ lsr r0, r0, #8
+ tst r0, #1 /* only need for cluster 0 */
+ bne _exit_init_l2_a15
+
+ mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */
+ and r1, r0, #7
+ cmp r1, #3 /* has already been set up */
+ bicne r0, r0, #0xe7
+ orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
+#if defined(CONFIG_R8A7790)
+ orrne r0, r0, #0x20 /* L2CTLR[5] */
+#endif
+ mcrne p15, 1, r0, c9, c0, 2
+
+ b _exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x40
+ mcr p15, 0, r0, c1, c0, 1
+#endif
+
+_exit_init_l2_a15:
+ ldr r3, =(SYS_INIT_SP_ADDR)
+ sub sp, r3, #4
+ str lr, [sp]
+
+ /* initialize system */
+ bl s_init
+
+ ldr lr, [sp]
+#endif
+ mov pc, lr
+ nop
+ENDPROC(lowlevel_init)
+ .ltorg
diff --git a/arch/arm/mach-renesas/lowlevel_init_gen3.S b/arch/arm/mach-renesas/lowlevel_init_gen3.S
new file mode 100644
index 0000000..0d77800
--- /dev/null
+++ b/arch/arm/mach-renesas/lowlevel_init_gen3.S
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
+ * This file is lowlevel initialize routine.
+ *
+ * (C) Copyright 2015 Renesas Electronics Corporation
+ *
+ * This file is based on the arch/arm/cpu/armv8/start.S
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+.align 8
+.globl rcar_atf_boot_args
+rcar_atf_boot_args:
+ .dword 0
+ .dword 0
+ .dword 0
+ .dword 0
+
+ENTRY(save_boot_params)
+ adr x8, rcar_atf_boot_args
+ stp x0, x1, [x8], #16
+ stp x2, x3, [x8], #16
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+.pushsection .text.s_init, "ax"
+WEAK(s_init)
+ ret
+ENDPROC(s_init)
+.popsection
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+#ifndef CONFIG_ARMV8_MULTIENTRY
+ /*
+ * For single-entry systems the lowlevel init is very simple.
+ */
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+ branch_if_slave x0, 1f
+ ldr x0, =GICD_BASE
+ bl gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+ ldr x0, =GICR_BASE
+ bl gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+ branch_if_master x0, 2f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent salves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
+
+ /*
+ * All slaves will enter EL2 and optionally EL1.
+ */
+ adr x4, lowlevel_in_el2
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x4, lowlevel_in_el1
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+ bl s_init
+
+2:
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-renesas/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c
new file mode 100644
index 0000000..4dff9e0
--- /dev/null
+++ b/arch/arm/mach-renesas/memmap-gen3.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RCar Gen3 memory map tables
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ */
+
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <cpu_func.h>
+
+#define GEN3_NR_REGIONS 16
+
+static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x03F00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E00000UL,
+ .phys = 0x47E00000UL,
+ .size = 0x78200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xc0000000UL,
+ .phys = 0xc0000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0xf00000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = gen3_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void enable_caches(void)
+{
+ u64 start, size;
+ int bank, i = 0;
+
+ /* Create map for RPC access */
+ gen3_mem_map[i].virt = 0x0ULL;
+ gen3_mem_map[i].phys = 0x0ULL;
+ gen3_mem_map[i].size = 0x40000000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ i++;
+
+ /* Generate entires for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Skip DRAM above 4 GiB */
+ if (start >> 32ULL)
+ continue;
+
+ /* Mark memory reserved by ATF as cacheable too. */
+ if (start == 0x48000000) {
+ /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
+ gen3_mem_map[i].virt = 0x40000000ULL;
+ gen3_mem_map[i].phys = 0x40000000ULL;
+ gen3_mem_map[i].size = 0x03F00000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+
+ start = 0x47E00000ULL;
+ size += 0x00200000ULL;
+ }
+
+ gen3_mem_map[i].virt = start;
+ gen3_mem_map[i].phys = start;
+ gen3_mem_map[i].size = size;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+ }
+
+ /* Create map for register access */
+ gen3_mem_map[i].virt = 0xc0000000ULL;
+ gen3_mem_map[i].phys = 0xc0000000ULL;
+ gen3_mem_map[i].size = 0x40000000ULL;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ i++;
+
+ /* Generate entires for DRAM in 64bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Skip DRAM below 4 GiB */
+ if (!(start >> 32ULL))
+ continue;
+
+ gen3_mem_map[i].virt = start;
+ gen3_mem_map[i].phys = start;
+ gen3_mem_map[i].size = size;
+ gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ i++;
+ }
+
+ /* Zero out the remaining regions. */
+ for (; i < GEN3_NR_REGIONS; i++) {
+ gen3_mem_map[i].virt = 0;
+ gen3_mem_map[i].phys = 0;
+ gen3_mem_map[i].size = 0;
+ gen3_mem_map[i].attrs = 0;
+ }
+
+ if (!icache_status())
+ icache_enable();
+
+ dcache_enable();
+}
diff --git a/arch/arm/mach-renesas/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c
new file mode 100644
index 0000000..9934a77
--- /dev/null
+++ b/arch/arm/mach-renesas/memmap-rzg2l.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/G2L family memory map tables
+ *
+ * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include <asm/armv8/mmu.h>
+#include <asm/global_data.h>
+#include <asm/u-boot.h>
+#include <cpu_func.h>
+
+#define RZG2L_NR_REGIONS 16
+
+/*
+ * RZ/G2L supports up to 4 GiB RAM starting at 0x40000000, of
+ * which the first 128 MiB is reserved by TF-A.
+ */
+static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x03F00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E00000UL,
+ .phys = 0x47E00000UL,
+ .size = 0xF8200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rzg2l_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define debug_memmap(i, map) \
+ debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx, attrs=0x%llx\n", \
+ i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
+
+void enable_caches(void)
+{
+ unsigned int bank, i = 0;
+ u64 start, size;
+
+ /* Create map for register access */
+ rzg2l_mem_map[i].virt = 0x0ULL;
+ rzg2l_mem_map[i].phys = 0x0ULL;
+ rzg2l_mem_map[i].size = 0x40000000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ /* Generate entries for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty DRAM banks */
+ if (!size)
+ continue;
+
+ /* Mark memory reserved by ATF as cacheable too. */
+ if (start == 0x48000000) {
+ /* Unmark protection area (0x43F00000 to 0x47DFFFFF) */
+ rzg2l_mem_map[i].virt = 0x40000000ULL;
+ rzg2l_mem_map[i].phys = 0x40000000ULL;
+ rzg2l_mem_map[i].size = 0x03F00000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ start = 0x47E00000ULL;
+ size += 0x00200000ULL;
+ }
+
+ rzg2l_mem_map[i].virt = start;
+ rzg2l_mem_map[i].phys = start;
+ rzg2l_mem_map[i].size = size;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+ }
+
+ /* Zero out the remaining regions. */
+ for (; i < RZG2L_NR_REGIONS; i++) {
+ rzg2l_mem_map[i].virt = 0;
+ rzg2l_mem_map[i].phys = 0;
+ rzg2l_mem_map[i].size = 0;
+ rzg2l_mem_map[i].attrs = 0;
+ debug_memmap(i, rzg2l_mem_map);
+ }
+
+ if (!icache_status())
+ icache_enable();
+
+ dcache_enable();
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+
+ return 0;
+}
diff --git a/arch/arm/mach-renesas/psci-r8a779a0.c b/arch/arm/mach-renesas/psci-r8a779a0.c
new file mode 100644
index 0000000..b6c49e7
--- /dev/null
+++ b/arch/arm/mach-renesas/psci-r8a779a0.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file implements basic PSCI support for Renesas r8a779a0 SoC
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ */
+
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+
+int __secure psci_features(u32 function_id, u32 psci_fid)
+{
+ switch (psci_fid) {
+ case ARM_PSCI_0_2_FN_PSCI_VERSION:
+ case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+ return 0x0;
+ }
+ /* case ARM_PSCI_0_2_FN_CPU_ON: */
+ /* case ARM_PSCI_0_2_FN_CPU_OFF: */
+ /* case ARM_PSCI_0_2_FN_AFFINITY_INFO: */
+ /* case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: */
+ /* case ARM_PSCI_0_2_FN_SYSTEM_OFF: */
+ return ARM_PSCI_RET_NI;
+}
+
+u32 __secure psci_version(void)
+{
+ return ARM_PSCI_VER_0_2;
+}
+
+#define RST_BASE 0xE6160000 /* Domain0 */
+#define RST_SRESCR0 (RST_BASE + 0x18)
+#define RST_SPRES 0x5AA58000
+
+void __secure __noreturn psci_system_reset(void)
+{
+ writel(RST_SPRES, RST_SRESCR0);
+
+ while (1)
+ ;
+}
+
+int psci_update_dt(void *fdt)
+{
+ return 0;
+}