spi: stm32_qspi: Add chip select management
Quad-SPI interface is able to manage 2 spi nor devices.
FSEL bit selects the flash memory to be addressed in single flash mode.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c
index 9fe8b29..56ea591 100644
--- a/drivers/spi/stm32_qspi.c
+++ b/drivers/spi/stm32_qspi.c
@@ -155,6 +155,8 @@
/* default SCK frequency, unit: HZ */
#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
+#define STM32_MAX_NORCHIP 2
+
struct stm32_qspi_platdata {
u32 base;
u32 memory_map;
@@ -212,6 +214,12 @@
fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
}
+static void _stm32_qspi_set_cs(struct stm32_qspi_priv *priv, unsigned int cs)
+{
+ clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL,
+ cs ? STM32_QSPI_CR_FSEL : 0);
+}
+
static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
{
unsigned int ccr_reg = 0;
@@ -497,10 +505,17 @@
struct stm32_qspi_priv *priv;
struct udevice *bus;
struct spi_flash *flash;
+ struct dm_spi_slave_platdata *slave_plat;
bus = dev->parent;
priv = dev_get_priv(bus);
flash = dev_get_uclass_priv(dev);
+ slave_plat = dev_get_parent_platdata(dev);
+
+ if (slave_plat->cs >= STM32_MAX_NORCHIP)
+ return -ENODEV;
+
+ _stm32_qspi_set_cs(priv, slave_plat->cs);
_stm32_qspi_set_flash_size(priv, flash->size);