tree 48832d610d61ee6e3a029ae66083c63ac7ef7dc5
parent bae46f3d3d89ae07b6985f5fe7f01a02039e9345
author Svyatoslav Ryhel <clamor95@gmail.com> 1706030180 +0200
committer Anatolij Gustschin <agust@denx.de> 1713683221 +0200

video: tegra20: dc: add PLLD2 parent support

T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.

Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565
Tested-by: Ion Agorria <ion@agorria.com> # HTC One X
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>