tree cabdaa860480f895cccc6600f3454a751329c13c
parent 05f1ea016b4881f3544f94c5b417cac64282c916
author Stefan Roese <sr@denx.de> 1154104498 +0200
committer Stefan Roese <sr@denx.de> 1154104498 +0200

PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006