diff --git a/arch/riscv/cpu/jh7110/Makefile b/arch/riscv/cpu/jh7110/Makefile
new file mode 100644
index 0000000..951c956
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 StarFive Technology Co., Ltd.
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += cpu.o
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/jh7110/cpu.c b/arch/riscv/cpu/jh7110/cpu.c
new file mode 100644
index 0000000..1d7c026
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/cpu.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <asm/cache.h>
+#include <irq_func.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+	disable_interrupts();
+
+	cache_flush();
+
+	return 0;
+}
diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c
new file mode 100644
index 0000000..2ad3f20
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang <yanhong.wang@starfivetech.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+	/*
+	 * Ensure that we run from first 4GB so that all
+	 * addresses used by U-Boot are 32bit addresses.
+	 *
+	 * This in-turn ensures that 32bit DMA capable
+	 * devices work fine because DMA mapping APIs will
+	 * provide 32bit DMA addresses only.
+	 */
+	if (IS_ENABLED(CONFIG_64BIT) && gd->ram_top > SZ_4G)
+		return SZ_4G;
+
+	return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
new file mode 100644
index 0000000..104f0fe
--- /dev/null
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Author: Yanhong Wang<yanhong.wang@starfivetech.com>
+ */
+
+#include <asm/csr.h>
+#include <asm/sections.h>
+#include <dm.h>
+#include <log.h>
+
+#define CSR_U74_FEATURE_DISABLE	0x7c1
+#define L2_LIM_MEM_END	0x81FFFFFUL
+
+int spl_soc_init(void)
+{
+	int ret;
+	struct udevice *dev;
+
+	/* DDR init */
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+void harts_early_init(void)
+{
+	ulong *ptr;
+	u8 *tmp;
+	ulong len, remain;
+	/*
+	 * Feature Disable CSR
+	 *
+	 * Clear feature disable CSR to '0' to turn on all features for
+	 * each core. This operation must be in M-mode.
+	 */
+	if (CONFIG_IS_ENABLED(RISCV_MMODE))
+		csr_write(CSR_U74_FEATURE_DISABLE, 0);
+
+	/* clear L2 LIM  memory
+	 * set __bss_end to 0x81FFFFF region to zero
+	 * The L2 Cache Controller supports ECC. ECC is applied to SRAM.
+	 * If it is not cleared, the ECC part is invalid, and an ECC error
+	 * will be reported when reading data.
+	 */
+	ptr = (ulong *)&__bss_end;
+	len = L2_LIM_MEM_END - (ulong)&__bss_end;
+	remain = len % sizeof(ulong);
+	len /= sizeof(ulong);
+
+	while (len--)
+		*ptr++ = 0;
+
+	/* clear the remain bytes */
+	if (remain) {
+		tmp = (u8 *)ptr;
+		while (remain--)
+			*tmp++ = 0;
+	}
+}