OMAP242x H4 board update
- fix for ES2 differences.
- switch to using the cfi_flash driver.
- fix SRAM build address.
- fix for GP device operation.
- unlock SRAM for GP devices.
- display more device information.
- fix potential deadlock in omap24xx_i2c driver.
- fix DLL load values to match dpllout*1 operation.
- fix 2nd chip select init for combo DDR device.
- add support for CFI Intel 28F256L18 on H4 board.
Patch by Richard Woodruff, 03 Mar 2005
diff --git a/include/asm-arm/arch-arm1136/mem.h b/include/asm-arm/arch-arm1136/mem.h
index dfaf568..c81f1c4 100644
--- a/include/asm-arm/arch-arm1136/mem.h
+++ b/include/asm-arm/arch-arm1136/mem.h
@@ -13,7 +13,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -25,8 +25,8 @@
#ifndef _OMAP24XX_MEM_H_
#define _OMAP24XX_MEM_H_
-#define SDRC_CS0_OSET 0x0
-#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
+#define SDRC_CS0_OSET 0x0
+#define SDRC_CS1_OSET 0x30 /* mirror CS1 regs appear offset 0x30 from CS0 */
#ifndef __ASSEMBLY__
/* struct's for holding data tables for current boards, they are getting used
@@ -40,8 +40,7 @@
u32 sdrc_rfr_ctrl;
u32 sdrc_mr_0_ddr;
u32 sdrc_mr_0_sdr;
- u32 sdrc_dlla_ctrl;
- u32 sdrc_dllb_ctrl;
+ u32 sdrc_dllab_ctrl;
} /*__attribute__ ((packed))*/;
typedef struct sdrc_data_s sdrc_data_t;
@@ -49,129 +48,109 @@
STACKED = 0,
IP_DDR = 1,
COMBO_DDR = 2,
- IP_SDR = 3,
+ IP_SDR = 3,
} mem_t;
#endif
/* Slower full frequency range default timings for x32 operation*/
-#define H4_2420_SDRC_SHARING 0x00000100
+#define H4_2420_SDRC_SHARING 0x00000100
#define H4_2420_SDRC_MDCFG_0_SDR 0x00D04010 /* discrete sdr module */
#define H4_2420_SDRC_MR_0_SDR 0x00000031
#define H4_2420_SDRC_MDCFG_0_DDR 0x01702011 /* descrite ddr module */
#define H4_2420_COMBO_MDCFG_0_DDR 0x00801011 /* combo module */
#define H4_2420_SDRC_MR_0_DDR 0x00000032
-#ifndef CONFIG_OPTIMIZE_DDR
-# define H4_2420_SDRC_ACTIM_CTRLA_0 0x9bead909
-# define H4_2420_SDRC_ACTIM_CTRLB_0 0x00000014
-# define H4_2420_SDRC_RFR_CTRL_ES1 0x00002401
-# define H4_2420_SDRC_RFR_CTRL 0x0002da01
-#endif
-#define H4_2420_SDRC_DLLA_CTRL 0x0000E307 /* DLL value used for 50MHz */
-#define H4_2420_SDRC_DLLB_CTRL 0x0000E307 /* allow DPLLout*1 to work */
-
#define H4_2422_SDRC_SHARING 0x00004b00
#define H4_2422_SDRC_MDCFG_0_DDR 0x00801011 /* stacked ddr on 2422 */
-#ifndef CONFIG_OPTIMIZE_DDR
-# define H4_2422_SDRC_ACTIM_CTRLA_0 0x9BEAD909
-# define H4_2422_SDRC_ACTIM_CTRLB_0 0x00000020
-# define H4_2422_SDRC_RFR_CTRL_ES1 0x00002401
-# define H4_2422_SDRC_RFR_CTRL 0x0002da01
-#endif
#define H4_2422_SDRC_MR_0_DDR 0x00000032
-#define H4_2422_SDRC_DLLA_CTRL 0x00007307
-#define H4_2422_SDRC_DLLB_CTRL 0x00007307
-/* optimized timings */
+/* ES1 work around timings */
+#define H4_242x_SDRC_ACTIM_CTRLA_0_ES1 0x9bead909 /* 165Mhz for use with 100/133 */
+#define H4_242x_SDRC_ACTIM_CTRLB_0_ES1 0x00000020
+#define H4_242x_SDRC_RFR_CTRL_ES1 0x00002401 /* use over refresh for ES1 */
+
+/* optimized timings good for current shipping parts */
#define H4_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x5A59B485
#define H4_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000e
-#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settigs */
-#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
-#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01 /* this is not optimal yet */
-#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
+#define H4_242X_SDRC_ACTIM_CTRLA_0_133MHz 0x8BA6E6C8 /* temp warn 0 settings */
+#define H4_242X_SDRC_ACTIM_CTRLB_0_133MHz 0x00000010 /* temp warn 0 settings */
+#define H4_242X_SDRC_RFR_CTRL_100MHz 0x0002da01
+#define H4_242X_SDRC_RFR_CTRL_133MHz 0x0003de01
+#define H4_242x_SDRC_DLLAB_CTRL_100MHz 0x0000980E /* 72deg, allow DPLLout*1 to work (combo)*/
+#define H4_242x_SDRC_DLLAB_CTRL_133MHz 0x0000690E /* 72deg, for ES2 */
-#ifdef CONFIG_OPTIMIZE_DDR
-# ifdef PRCM_CONFIG_II
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_100MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
-# elif PRCM_CONFIG_III
-# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
-# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
-# define H4_2420_SDRC_RFR_CTRL_ES1 H4_242X_SDRC_RFR_CTRL_133MHz
-# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
-# endif
-# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_2420_SDRC_ACTIM_CTRLA_0
-# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_2420_SDRC_ACTIM_CTRLB_0
-# define H4_2422_SDRC_RFR_CTRL_ES1 H4_2420_SDRC_RFR_CTRL_ES1
-# define H4_2422_SDRC_RFR_CTRL H4_2420_SDRC_RFR_CTRL
+#ifdef PRCM_CONFIG_II
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
+#elif PRCM_CONFIG_III
+# define H4_2420_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_133MHz
+# define H4_2420_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_133MHz
+# define H4_2420_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_133MHz
+# define H4_2420_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_133MHz
+# define H4_2422_SDRC_ACTIM_CTRLA_0 H4_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define H4_2422_SDRC_ACTIM_CTRLB_0 H4_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define H4_2422_SDRC_RFR_CTRL H4_242X_SDRC_RFR_CTRL_100MHz
+# define H4_2422_SDRC_DLLAB_CTRL H4_242x_SDRC_DLLAB_CTRL_100MHz
#endif
/* GPMC settings */
-#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
-#ifdef CFG_NAND_BOOT
-#define H4_24XX_GPMC_CONFIG1_0 0x0
-#define H4_24XX_GPMC_CONFIG2_0 0x00141400
-#define H4_24XX_GPMC_CONFIG3_0 0x00141400
-#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-#else
-#define H4_24XX_GPMC_CONFIG1_0 0x3
-#define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
-#define H4_24XX_GPMC_CONFIG3_0 0x00050502
-#define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
-#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-#endif
-#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
+# ifdef CFG_NAND_BOOT
+# define H4_24XX_GPMC_CONFIG1_0 0x0
+# define H4_24XX_GPMC_CONFIG2_0 0x00141400
+# define H4_24XX_GPMC_CONFIG3_0 0x00141400
+# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* else NOR */
+# define H4_24XX_GPMC_CONFIG1_0 0x3
+# define H4_24XX_GPMC_CONFIG2_0 0x000f0f01
+# define H4_24XX_GPMC_CONFIG3_0 0x00050502
+# define H4_24XX_GPMC_CONFIG4_0 0x0C060C06
+# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1 0x00011000
+# define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
+# define H4_24XX_GPMC_CONFIG3_1 0x00080802
+# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
+# define H4_24XX_GPMC_CONFIG6_1 0x000003C2
+# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
-#define H4_24XX_GPMC_CONFIG1_1 0x00011000
-#define H4_24XX_GPMC_CONFIG2_1 0x001F1F00
-#define H4_24XX_GPMC_CONFIG3_1 0x00080802
-#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-#define H4_24XX_GPMC_CONFIG5_1 0x031A1F1F
-#define H4_24XX_GPMC_CONFIG6_1 0x000003C2
-#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif
+#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+# define H4_24XX_GPMC_CONFIG1_0 0x0
+# define H4_24XX_GPMC_CONFIG2_0 0x00141400
+# define H4_24XX_GPMC_CONFIG3_0 0x00141400
+# define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define H4_24XX_GPMC_CONFIG5_0 0x010C1414
+# define H4_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* NOR boot */
+# define H4_24XX_GPMC_CONFIG1_0 0x3
+# define H4_24XX_GPMC_CONFIG2_0 0x00151501
+# define H4_24XX_GPMC_CONFIG3_0 0x00060602
+# define H4_24XX_GPMC_CONFIG4_0 0x10081008
+# define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
+# define H4_24XX_GPMC_CONFIG6_0 0x000004c4
+# endif /* endif CFG_NAND_BOOT */
+# define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
+# define H4_24XX_GPMC_CONFIG1_1 0x00011000
+# define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
+# define H4_24XX_GPMC_CONFIG3_1 0x00080803
+# define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
+# define H4_24XX_GPMC_CONFIG6_1 0x000004C4
+# define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
-#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
-#ifdef CFG_NAND_BOOT
-#define H4_24XX_GPMC_CONFIG1_0 0x0
-#define H4_24XX_GPMC_CONFIG2_0 0x00141400
-#define H4_24XX_GPMC_CONFIG3_0 0x00141400
-#define H4_24XX_GPMC_CONFIG4_0 0x0F010F01
-#define H4_24XX_GPMC_CONFIG5_0 0x010C1414
-#define H4_24XX_GPMC_CONFIG6_0 0x00000A80
-#else
-#define H4_24XX_GPMC_CONFIG1_0 0x3
-#define H4_24XX_GPMC_CONFIG2_0 0x00151501
-#define H4_24XX_GPMC_CONFIG3_0 0x00060602
-#define H4_24XX_GPMC_CONFIG4_0 0x10081008
-#define H4_24XX_GPMC_CONFIG5_0 0x01131F1F
-#define H4_24XX_GPMC_CONFIG6_0 0x000004c4
-#endif
-#define H4_24XX_GPMC_CONFIG7_0 (0x00000C40|(H4_CS0_BASE >> 24))
-
-#define H4_24XX_GPMC_CONFIG1_1 0x00011000
-#define H4_24XX_GPMC_CONFIG2_1 0x001f1f01
-#define H4_24XX_GPMC_CONFIG3_1 0x00080803
-#define H4_24XX_GPMC_CONFIG4_1 0x1C091C09
-#define H4_24XX_GPMC_CONFIG5_1 0x041f1F1F
-#define H4_24XX_GPMC_CONFIG6_1 0x000004C4
-#define H4_24XX_GPMC_CONFIG7_1 (0x00000F40|(H4_CS1_BASE >> 24))
-#endif
-
-#ifdef CONFIG_APTIX /* SDRC-SDR for Aptix x16 */
-#define VAL_H4_SDRC_SHARING_16 0x00002400 /* No-Tristate, 16bit on D31-D16, CS1=dont care */
-#define VAL_H4_SDRC_SHARING 0x00000100
-#define VAL_H4_SDRC_MCFG_0_16 0x00901000 /* SDR-SDRAM,External,x16 bit */
-#define VAL_H4_SDRC_MCFG_0 0x01702011
-#define VAL_H4_SDRC_MR_0 0x00000029 /* Burst=2, Serial Mode, CAS 3*/
-#define VAL_H4_SDRC_RFR_CTRL_0 0x00001703 /* refresh time */
-#define VAL_H4_SDRC_DCDL2_CTRL 0x5A59B485
-#endif
-
-#endif
+#endif /* endif _OMAP24XX_MEM_H_ */