| commit | e118f5ef27d9db68832d334ec07084233f0beffa | [log] [tgz] |
|---|---|---|
| author | Rick Chen <rick@andestech.com> | Wed Aug 28 18:46:06 2019 +0800 |
| committer | Andes <uboot@andestech.com> | Tue Sep 03 09:31:03 2019 +0800 |
| tree | ec0822a0d677e1e2fc8c2d4491894373d5857d33 | |
| parent | a7af286a3e0cc7f5c2468e0e3574c86bfe9cc98a [diff] |
dm: cache: add v5l2 cache controller driver Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>