rockchip: rk3588: Update USB3 related nodes in u-boot.dtsi
The USB3 related DT nodes in SoC u-boot.dtsi is slightly different from
the final nodes being targeted for Linux kernel v6.10.
Sync USB3 related nodes from Linux maintainer v6.10-rockchip-dts64-1 tag
to prepare for migration of RK3588 to use OF_UPSTREAM.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index d3c2579..e9d38d5 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -27,7 +27,7 @@
<&cru ACLK_USB3OTG0>;
clock-names = "ref_clk", "suspend_clk", "bus_clk";
dr_mode = "otg";
- phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
power-domains = <&power RK3588_PD_USB>;
@@ -58,22 +58,21 @@
};
usb2phy0_grf: syscon@fd5d0000 {
- compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
- "simple-mfd";
+ compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
reg = <0x0 0xfd5d0000 0x0 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
- u2phy0: usb2-phy@0 {
+ u2phy0: usb2phy@0 {
compatible = "rockchip,rk3588-usb2phy";
reg = <0x0 0x10>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
- resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
- reset-names = "phy", "apb";
+ #clock-cells = <0>;
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
clock-output-names = "usb480m_phy0";
- #clock-cells = <0>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
status = "disabled";
u2phy0_otg: otg-port {
@@ -91,10 +90,7 @@
usbdp_phy0: phy@fed80000 {
compatible = "rockchip,rk3588-usbdp-phy";
reg = <0x0 0xfed80000 0x0 0x10000>;
- rockchip,u2phy-grf = <&usb2phy0_grf>;
- rockchip,usb-grf = <&usb_grf>;
- rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
- rockchip,vo-grf = <&vo0_grf>;
+ #phy-cells = <1>;
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
<&cru CLK_USBDP_PHY0_IMMORTAL>,
<&cru PCLK_USBDPPHY0>,
@@ -106,17 +102,11 @@
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
<&cru SRST_P_USBDPPHY0>;
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+ rockchip,u2phy-grf = <&usb2phy0_grf>;
+ rockchip,usb-grf = <&usb_grf>;
+ rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
status = "disabled";
-
- usbdp_phy0_dp: dp-port {
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usbdp_phy0_u3: usb3-port {
- #phy-cells = <0>;
- status = "disabled";
- };
};
};