Merge git://git.denx.de/u-boot-dm
diff --git a/README b/README
index 075d919..a4a9c3b 100644
--- a/README
+++ b/README
@@ -1015,7 +1015,7 @@
CONFIG_RTC_DS164x - use Dallas DS164x RTC
CONFIG_RTC_ISL1208 - use Intersil ISL1208 RTC
CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC
- CONFIG_SYS_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
+ CONFIG_RTC_DS1337_NOOSC - Turn off the OSC output for DS1337
CONFIG_SYS_RV3029_TCR - enable trickle charger on
RV3029 RTC.
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 8cae291..e8d7d54 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -36,12 +36,6 @@
#define TCFG_RESET BIT(0) /* software reset */
#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
#define TCFG_IDLEMOD_SHIFT (2) /* power management */
-/* device type */
-#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
/* cpu-id for AM43XX AM33XX and TI81XX family */
#define AM437X 0xB98C
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 0dafb9e..d2c5df8 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -41,6 +41,9 @@
unsigned char boot_device;
unsigned char reset_reason;
};
+
+#define DEVICE_TYPE_SHIFT 0x8
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#endif
#endif
diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h
index db763e4..8933f54 100644
--- a/arch/arm/include/asm/arch-omap3/omap.h
+++ b/arch/arm/include/asm/arch-omap3/omap.h
@@ -91,6 +91,9 @@
unsigned int s32k_cr; /* 0x10 */
};
+#define DEVICE_TYPE_SHIFT 0x8
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+
#endif /* __ASSEMBLY__ */
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index b86a776..1a3ff7d 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -100,7 +100,6 @@
#define DEVICE_TYPE_SHIFT (0x8)
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
-#define DEVICE_GP 0x3
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 8f31da1..2f005dd 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -127,7 +127,6 @@
#define DEVICE_TYPE_SHIFT 0x6
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
-#define DEVICE_GP 0x3
/* Output impedance control */
#define ds_120_ohm 0x0
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 6aa5e91..2419062 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -34,7 +34,9 @@
#define SUNXI_MS_BASE 0x01c07000
#define SUNXI_TVD_BASE 0x01c08000
#define SUNXI_CSI0_BASE 0x01c09000
+#ifndef CONFIG_MACH_SUNXI_H3_H5
#define SUNXI_TVE0_BASE 0x01c0a000
+#endif
#define SUNXI_EMAC_BASE 0x01c0b000
#define SUNXI_LCD0_BASE 0x01c0C000
#define SUNXI_LCD1_BASE 0x01c0d000
@@ -161,10 +163,18 @@
/* module sram */
#define SUNXI_SRAM_C_BASE 0x01d00000
+#ifndef CONFIG_MACH_SUN8I_H3
#define SUNXI_DE_FE0_BASE 0x01e00000
+#else
+#define SUNXI_TVE0_BASE 0x01e00000
+#endif
#define SUNXI_DE_FE1_BASE 0x01e20000
#define SUNXI_DE_BE0_BASE 0x01e60000
+#ifndef CONFIG_MACH_SUN50I_H5
#define SUNXI_DE_BE1_BASE 0x01e40000
+#else
+#define SUNXI_TVE0_BASE 0x01e40000
+#endif
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h
index b5875f9..359cacd 100644
--- a/arch/arm/include/asm/arch-sunxi/display2.h
+++ b/arch/arm/include/asm/arch-sunxi/display2.h
@@ -90,6 +90,23 @@
u32 ovl_size;
};
+struct de_csc {
+ u32 csc_ctl;
+ u8 res[0xc];
+ u32 coef11;
+ u32 coef12;
+ u32 coef13;
+ u32 coef14;
+ u32 coef21;
+ u32 coef22;
+ u32 coef23;
+ u32 coef24;
+ u32 coef31;
+ u32 coef32;
+ u32 coef33;
+ u32 coef34;
+};
+
/*
* DE register constants.
*/
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index f989983..7fb322a 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -484,6 +484,7 @@
u32 ctrl_core_sma_sw_1;
};
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
struct dpll_params {
u32 m;
u32 n;
@@ -516,6 +517,7 @@
u32 cm_div_h23_dpll;
u32 cm_div_h24_dpll;
};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
struct dplls {
const struct dpll_params *mpu;
@@ -539,6 +541,7 @@
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
enum {
OPP_LOW,
OPP_NOM,
@@ -584,6 +587,7 @@
struct volts eve;
struct volts iva;
};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
@@ -595,6 +599,8 @@
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const am33xx_ctrl;
+extern struct omap_sys_ctrl_regs const omap3_ctrl;
extern struct omap_sys_ctrl_regs const omap4_ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
@@ -611,6 +617,7 @@
const struct dpll_params *get_usb_dpll_params(struct dplls const *);
const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
@@ -619,6 +626,7 @@
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
@@ -630,7 +638,9 @@
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
void scale_vcores(struct vcores_data const *);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
@@ -750,7 +760,6 @@
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
*/
-#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
#define EMU_DEVICE 0x1
#define HS_DEVICE 0x2
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 5d7f7e6..0e67470 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -29,6 +29,7 @@
BOOT_DEVICE_I2C,
BOOT_DEVICE_BOARD,
BOOT_DEVICE_DFU,
+ BOOT_DEVICE_XIP,
BOOT_DEVICE_NONE
};
#endif
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 704849b..b3e5d24 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -360,6 +360,7 @@
#ifdef CONFIG_CPU_V7M
ulong addr = (ulong)kernel_entry | 1;
kernel_entry = (void *)addr;
+ dcache_disable();
#endif
s = getenv("machid");
if (s) {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d161b51..683cdb9 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -2,57 +2,7 @@
choice
prompt "OMAP2+ platform select"
- default TARGET_BRXRE1
-
-config TARGET_BRXRE1
- bool "Support BRXRE1"
- select BOARD_LATE_INIT
-
-config TARGET_BRPPT1
- bool "Support BRPPT1"
- select BOARD_LATE_INIT
-
-config TARGET_DRACO
- bool "Support draco"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_THUBAN
- bool "Support thuban"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_RASTABAN
- bool "Support rastaban"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_ETAMIN
- bool "Support etamin"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_PXM2
- bool "Support pxm2"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_RUT
- bool "Support rut"
- select BOARD_LATE_INIT
- select DM
- select DM_SERIAL
- select DM_GPIO
+ default OMAP34XX
config OMAP34XX
bool "OMAP34XX SoC"
@@ -151,9 +101,6 @@
protocols, optional 3D graphics and an optional customer
programmable secure boot.
-config TARGET_CM_T43
- bool "Support cm_t43"
-
endchoice
config SYS_MPUCLK
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index aa3986d..d43085c 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -20,6 +20,7 @@
endif
obj-y += utils.o
+obj-y += sysinfo-common.o
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
obj-y += hwinit-common.o
obj-y += clocks-common.o
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 36ec134..d8abba9 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -26,7 +26,6 @@
choice
prompt "AM33xx board select"
- optional
config TARGET_AM335X_EVM
bool "Support am335x_evm"
@@ -104,6 +103,14 @@
For more information, visit: http://birdland.com/oem
+config TARGET_BRXRE1
+ bool "Support BRXRE1"
+ select BOARD_LATE_INIT
+
+config TARGET_BRPPT1
+ bool "Support BRPPT1"
+ select BOARD_LATE_INIT
+
config TARGET_CHILIBOARD
bool "Grinn chiliBoard"
select AM33XX_CHILISOM
@@ -117,6 +124,20 @@
select DM_SERIAL
select DM_GPIO
+config TARGET_DRACO
+ bool "Support draco"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_ETAMIN
+ bool "Support etamin"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
config TARGET_PCM051
bool "Support pcm051"
select DM
@@ -135,12 +156,43 @@
select DM_SERIAL
select DM_GPIO
+config TARGET_PXM2
+ bool "Support pxm2"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_RASTABAN
+ bool "Support rastaban"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_RUT
+ bool "Support rut"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
+config TARGET_THUBAN
+ bool "Support thuban"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_SERIAL
+ select DM_GPIO
+
endchoice
endif
if AM43XX
+choice
+ prompt "AM43xx board select"
+
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select BOARD_LATE_INIT
@@ -171,6 +223,12 @@
evaluation module system that enables developers
to write software and develop hardware around
an AM43xx processor subsystem.
+
+config TARGET_CM_T43
+ bool "Support cm_t43"
+
+endchoice
+
endif
if AM43XX || AM33XX
diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile
index 1e4c04e..b2f8158 100644
--- a/arch/arm/mach-omap2/am33xx/Makefile
+++ b/arch/arm/mach-omap2/am33xx/Makefile
@@ -21,6 +21,8 @@
obj-$(CONFIG_TI816X) += ti816x_emif4.o
obj-y += board.o
obj-y += mux.o
+obj-y += prcm-regs.o
+obj-y += hw_data.o
obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c
index faf7d07..5f1bf9c 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -26,6 +26,7 @@
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
+#include <asm/omap_common.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
@@ -347,6 +348,7 @@
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
+ hw_data_init();
early_system_init();
board_early_init_f();
sdram_init();
@@ -361,6 +363,7 @@
int arch_cpu_init_dm(void)
{
+ hw_data_init();
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
early_system_init();
#endif
diff --git a/arch/arm/mach-omap2/am33xx/hw_data.c b/arch/arm/mach-omap2/am33xx/hw_data.c
new file mode 100644
index 0000000..63e55cf
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/hw_data.c
@@ -0,0 +1,19 @@
+/*
+ * HW data initialization for AM33xx.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+void hw_data_init(void)
+{
+ *ctrl = &am33xx_ctrl;
+}
diff --git a/arch/arm/mach-omap2/am33xx/prcm-regs.c b/arch/arm/mach-omap2/am33xx/prcm-regs.c
new file mode 100644
index 0000000..c9a3af6
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx/prcm-regs.c
@@ -0,0 +1,15 @@
+/*
+ * HW regs data for AM33xx.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const am33xx_ctrl = {
+ .control_status = CTRL_BASE + 0x40,
+};
diff --git a/arch/arm/mach-omap2/am33xx/sys_info.c b/arch/arm/mach-omap2/am33xx/sys_info.c
index 564bae6..ea434aa 100644
--- a/arch/arm/mach-omap2/am33xx/sys_info.c
+++ b/arch/arm/mach-omap2/am33xx/sys_info.c
@@ -51,16 +51,6 @@
}
/**
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (DEVICE_MASK);
- return mode >>= 8;
-}
-
-/**
* get_sysboot_value(void) - return SYS_BOOT[4:0]
*/
u32 get_sysboot_value(void)
diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c
index c090442..7f6db3c 100644
--- a/arch/arm/mach-omap2/hwinit-common.c
+++ b/arch/arm/mach-omap2/hwinit-common.c
@@ -278,15 +278,6 @@
return 0;
}
-/*
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- return (readl((*ctrl)->control_status) &
- (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
-}
-
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile
index 06cc9f2..61a76b6 100644
--- a/arch/arm/mach-omap2/omap3/Makefile
+++ b/arch/arm/mach-omap2/omap3/Makefile
@@ -14,6 +14,8 @@
obj-y += boot.o
obj-y += clock.o
obj-y += sys_info.o
+obj-y += prcm-regs.o
+obj-y += hw_data.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
endif
diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c
index 01df579..cd8e302 100644
--- a/arch/arm/mach-omap2/omap3/board.c
+++ b/arch/arm/mach-omap2/omap3/board.c
@@ -173,6 +173,11 @@
return;
}
+void early_system_init(void)
+{
+ hw_data_init();
+}
+
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
@@ -181,6 +186,7 @@
void s_init(void)
{
watchdog_init();
+ early_system_init();
try_unlock_memory();
@@ -204,6 +210,7 @@
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
+ early_system_init();
mem_init();
}
#endif
diff --git a/arch/arm/mach-omap2/omap3/hw_data.c b/arch/arm/mach-omap2/omap3/hw_data.c
new file mode 100644
index 0000000..53b220a
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3/hw_data.c
@@ -0,0 +1,19 @@
+/*
+ * HW data initialization for OMAP3.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+void hw_data_init(void)
+{
+ *ctrl = &omap3_ctrl;
+}
diff --git a/arch/arm/mach-omap2/omap3/prcm-regs.c b/arch/arm/mach-omap2/omap3/prcm-regs.c
new file mode 100644
index 0000000..ca29ce9
--- /dev/null
+++ b/arch/arm/mach-omap2/omap3/prcm-regs.c
@@ -0,0 +1,15 @@
+/*
+ * HW regs data for OMAP3.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const omap3_ctrl = {
+ .control_status = OMAP34XX_CTRL_BASE + 0x2F0,
+};
diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c
index 7e6c263..155f5b2 100644
--- a/arch/arm/mach-omap2/omap3/sys_info.c
+++ b/arch/arm/mach-omap2/omap3/sys_info.c
@@ -17,6 +17,7 @@
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/bootm.h>
+#include <asm/omap_common.h>
#include <i2c.h>
#include <linux/compiler.h>
@@ -236,14 +237,6 @@
return (readl(&ctrl_base->status) & SYSBOOT_MASK);
}
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
-}
-
#ifdef CONFIG_DISPLAY_CPUINFO
/**
* Print CPU information
diff --git a/arch/arm/mach-omap2/sysinfo-common.c b/arch/arm/mach-omap2/sysinfo-common.c
new file mode 100644
index 0000000..1dc7051
--- /dev/null
+++ b/arch/arm/mach-omap2/sysinfo-common.c
@@ -0,0 +1,21 @@
+/*
+ * System information routines for all OMAP based boards.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/omap_common.h>
+
+/**
+ * Tell if device is GP/HS/EMU/TST.
+ */
+u32 get_device_type(void)
+{
+ return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >>
+ DEVICE_TYPE_SHIFT;
+}
diff --git a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
index 057bf3f..1fb0648 100644
--- a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
+++ b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
@@ -1,9 +1,9 @@
/*
* drivers/mmc/sh-sdhi.h
*
- * SD/MMC driver for Reneas rmobile ARM SoCs
+ * SD/MMC driver for Renesas rmobile ARM SoCs
*
- * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2013-2017 Renesas Electronics Corporation
* Copyright (C) 2008-2009 Renesas Solutions Corp.
*
* SPDX-License-Identifier: GPL-2.0
@@ -50,8 +50,10 @@
/* SDHI CMD VALUE */
#define CMD_MASK 0x0000ffff
#define SDHI_APP 0x0040
+#define SDHI_MMC_SEND_OP_COND 0x0701
#define SDHI_SD_APP_SEND_SCR 0x0073
#define SDHI_SD_SWITCH 0x1C06
+#define SDHI_MMC_SEND_EXT_CSD 0x1C08
/* SDHI_PORTSEL */
#define USE_1PORT (1 << 8) /* 1 port */
@@ -120,7 +122,10 @@
#define CLK_ENABLE (1 << 8)
/* SDHI_OPTION */
-#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */
+#define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */
+#define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */
+#define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */
+#define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */
/* SDHI_ERR_STS1 */
#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
@@ -162,7 +167,9 @@
#define CLKDEV_INIT 400000 /* 100 - 400 KHz */
/* For quirk */
-#define SH_SDHI_QUIRK_16BIT_BUF (1)
+#define SH_SDHI_QUIRK_16BIT_BUF BIT(0)
+#define SH_SDHI_QUIRK_64BIT_BUF BIT(1)
+
int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
#endif /* _SH_SDHI_H */
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index ec6b3ff..8f43714 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -8,6 +8,25 @@
config STM32F7
bool "stm32f7 family"
+ select SUPPORT_SPL
+ select SPL
+ select SPL_CLK
+ select SPL_DM
+ select SPL_DM_SEQ_ALIAS
+ select SPL_DRIVERS_MISC_SUPPORT
+ select SPL_GPIO_SUPPORT
+ select SPL_LIBCOMMON_SUPPORT
+ select SPL_LIBGENERIC_SUPPORT
+ select SPL_MTD_SUPPORT
+ select SPL_OF_CONTROL
+ select SPL_OF_LIBFDT
+ select SPL_OF_TRANSLATE
+ select SPL_OS_BOOT
+ select SPL_PINCTRL
+ select SPL_RAM
+ select SPL_SERIAL_SUPPORT
+ select SPL_SYS_MALLOC_SIMPLE
+ select SPL_XIP_SUPPORT
source "arch/arm/mach-stm32/stm32f4/Kconfig"
source "arch/arm/mach-stm32/stm32f1/Kconfig"
diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c
index cd969cb..ad97ffa 100644
--- a/board/mpl/common/pci.c
+++ b/board/mpl/common/pci.c
@@ -20,26 +20,35 @@
#include "piix4_pci.h"
#include "pci_parts.h"
+void pci_405gp_init(struct pci_controller *hose);
+
void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
- struct pci_config_table *entry)
+ struct pci_config_table *entry)
{
struct pci_pip405_config_entry *table;
int i;
- table = (struct pci_pip405_config_entry*) entry->priv[0];
+ table = (struct pci_pip405_config_entry *)entry->priv[0];
- for (i=0; table[i].width; i++)
- {
+ for (i = 0; table[i].width; i++) {
#ifdef DEBUG
printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
table[i].index, table[i].val, table[i].width);
#endif
- switch(table[i].width)
- {
- case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
- case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
- case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
+ switch (table[i].width) {
+ case 1:
+ pci_hose_write_config_byte(hose, dev,
+ table[i].index, table[i].val);
+ break;
+ case 2:
+ pci_hose_write_config_word(hose, dev,
+ table[i].index, table[i].val);
+ break;
+ case 4:
+ pci_hose_write_config_dword(hose, dev,
+ table[i].index, table[i].val);
+ break;
}
}
}
@@ -52,26 +61,24 @@
/*
* Write pci interrupt line register
*/
- if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
+ if (PCI_DEV(dev) == 0) /* Device0 = PPC405 -> skip */
return;
pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
if ((pin == 0) || (pin > 4))
- return;
+ return;
int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
#ifdef DEBUG
printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
- PCI_DEV(dev),dev,int_line,int_line);
+ PCI_DEV(dev), dev, int_line, int_line);
#endif
}
-extern void pci_405gp_init(struct pci_controller *hose);
-
static struct pci_controller hose = {
- config_table: pci_pip405_config_table,
- fixup_irq: pci_pip405_fixup_irq,
+config_table: pci_pip405_config_table,
+fixup_irq : pci_pip405_fixup_irq,
};
@@ -81,7 +88,8 @@
hose.fixup_irq = pci_pip405_fixup_irq;
hose.config_table = pci_pip405_config_table;
#ifdef DEBUG
- printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
+ printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",
+ pci_pip405_fixup_irq, pci_pip405_config_table, hose);
#endif
pci_405gp_init(&hose);
}
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 7a6d93c..fc4c60c 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <ram.h>
+#include <spl.h>
#include <asm/io.h>
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
@@ -36,16 +37,18 @@
}
int dram_init(void)
{
- struct udevice *dev;
int rv;
fdt_addr_t mr_base, mr_size;
+#ifndef CONFIG_SUPPORT_SPL
+ struct udevice *dev;
rv = uclass_get_device(UCLASS_RAM, 0, &dev);
if (rv) {
debug("DRAM init failed: %d\n", rv);
return rv;
}
+#endif
rv = get_memory_base_size(&mr_base, &mr_size);
if (rv)
return rv;
@@ -87,6 +90,37 @@
}
#endif
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_XIP;
+}
+
+#endif
u32 get_board_rev(void)
{
return 0;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 517965c..b5c4ed7 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -26,6 +26,7 @@
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
+#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/omap_mmc.h>
#include <i2c.h>
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f44103d..54f40e6 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -20,6 +20,7 @@
#include <asm/arch/ddr_defs.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
+#include <asm/omap_common.h>
#include "../common/board_detect.h"
#include "board.h"
#include <power/pmic.h>
@@ -421,6 +422,13 @@
printf("%s failure\n", __func__);
return;
}
+
+ /* Set DCDC3 (DDR) voltage */
+ if (tps65218_voltage_update(TPS65218_DCDC3,
+ TPS65218_DCDC3_VOLT_SEL_1350MV)) {
+ printf("%s failure\n", __func__);
+ return;
+ }
}
void scale_vcores_idk(u32 m)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 6d9ee20..0f70ef3 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -643,8 +643,8 @@
void recalibrate_iodelay(void)
{
const struct pad_conf_entry *pconf;
- const struct iodelay_cfg_entry *iod;
- int pconf_sz, iod_sz;
+ const struct iodelay_cfg_entry *iod, *delta_iod;
+ int pconf_sz, iod_sz, delta_iod_sz = 0;
int ret;
if (board_is_am572x_idk()) {
@@ -696,6 +696,9 @@
if (am571x_idk_needs_lcd()) {
pconf = core_padconf_array_vout_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
+ delta_iod = iodelay_cfg_array_am571x_idk_4port;
+ delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
+
} else {
pconf = core_padconf_array_icss1eth_am571x_idk;
pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
@@ -705,6 +708,10 @@
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
+ if (delta_iod_sz)
+ ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
+ delta_iod_sz);
+
err:
/* Closeup.. remove isolation */
__recalibrate_iodelay_end(ret);
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index aff274c..b4a71bd 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -67,8 +67,8 @@
{GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
{GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
- {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
- {VIN1B_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1b_clk1.gpio2_31 */
+ {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
+ {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */
{VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */
{VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */
{VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */
@@ -87,14 +87,14 @@
{VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */
{VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */
{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */
- {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */
+ {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.pr1_uart0_cts_n */
{VIN2A_VSYNC0, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */
- {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
- {VIN2A_D1, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
- {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */
- {VIN2A_D3, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */
- {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */
- {VIN2A_D5, (M8 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */
+ {VIN2A_D0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d2.uart10_rxd */
+ {VIN2A_D3, (M8 | PIN_OUTPUT)}, /* vin2a_d3.uart10_txd */
+ {VIN2A_D4, (M8 | PIN_INPUT_PULLUP)}, /* vin2a_d4.uart10_ctsn */
+ {VIN2A_D5, (M8 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.uart10_rtsn */
{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */
{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */
{VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */
@@ -113,40 +113,12 @@
{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
{VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_OUTPUT)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */
- {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */
- {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */
+ {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */
{RGMII0_TXC, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_OUTPUT | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
@@ -159,8 +131,8 @@
{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN)}, /* usb2_drvvbus.usb2_drvvbus */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */
{GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */
{GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */
@@ -169,48 +141,36 @@
{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */
- {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */
+ {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_fsx.i2c3_scl */
{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */
{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */
- {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.i2c5_sda */
- {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.i2c5_scl */
+ {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */
+ {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */
{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR8, (M14 | PIN_INPUT)}, /* mcasp1_axr8.gpio5_10 */
- {MCASP1_AXR9, (M14 | PIN_INPUT)}, /* mcasp1_axr9.gpio5_11 */
- {MCASP1_AXR10, (M14 | PIN_INPUT)}, /* mcasp1_axr10.gpio5_12 */
- {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr11.gpio4_17 */
- {MCASP1_AXR12, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
- {MCASP1_AXR13, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
- {MCASP1_AXR14, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
- {MCASP1_AXR15, (M1 | PIN_INPUT | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
- {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */
- {MCASP2_FSX, (M0 | PIN_INPUT)}, /* mcasp2_fsx.mcasp2_fsx */
- {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */
- {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */
- {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */
- {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */
- {MCASP2_AXR2, (M0 | PIN_INPUT)}, /* mcasp2_axr2.mcasp2_axr2 */
- {MCASP2_AXR3, (M0 | PIN_INPUT)}, /* mcasp2_axr3.mcasp2_axr3 */
- {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */
- {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */
- {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */
- {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */
+ {MCASP1_AXR8, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr8.gpio5_10 */
+ {MCASP1_AXR9, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr9.gpio5_11 */
+ {MCASP1_AXR10, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_axr10.gpio5_12 */
+ {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */
+ {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr12.mcasp7_axr0 */
+ {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr13.mcasp7_axr1 */
+ {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr14.mcasp7_aclkx */
+ {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)}, /* mcasp1_axr15.mcasp7_fsx */
{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */
- {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */
- {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */
- {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */
+ {MCASP3_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.mcasp3_fsx */
+ {MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr0.mcasp3_axr0 */
+ {MCASP3_AXR1, (M0 | PIN_INPUT_SLEW)}, /* mcasp3_axr1.mcasp3_axr1 */
{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_aclkx.uart8_rxd */
- {MCASP4_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */
- {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */
+ {MCASP4_FSX, (M3 | PIN_OUTPUT)}, /* mcasp4_fsx.uart8_txd */
+ {MCASP4_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr0.uart8_ctsn */
{MCASP4_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */
{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_aclkx.uart9_rxd */
- {MCASP5_FSX, (M3 | PIN_OUTPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */
- {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */
+ {MCASP5_FSX, (M3 | PIN_OUTPUT)}, /* mcasp5_fsx.uart9_txd */
+ {MCASP5_AXR0, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr0.uart9_ctsn */
{MCASP5_AXR1, (M3 | PIN_OUTPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
@@ -218,7 +178,7 @@
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
{GPIO6_10, (M10 | PIN_OUTPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */
{GPIO6_11, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */
{MMC3_CLK, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_clk.mmc3_clk */
@@ -227,31 +187,31 @@
{MMC3_DAT1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat1.mmc3_dat1 */
{MMC3_DAT2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat2.mmc3_dat2 */
{MMC3_DAT3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat3.mmc3_dat3 */
- {MMC3_DAT4, (M1 | PIN_OUTPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */
- {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */
- {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */
- {MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */
+ {MMC3_DAT4, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat4.mmc3_dat4 */
+ {MMC3_DAT5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat5.mmc3_dat5 */
+ {MMC3_DAT6, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat6.mmc3_dat6 */
+ {MMC3_DAT7, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* mmc3_dat7.mmc3_dat7 */
{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
{SPI1_CS0, (M14 | PIN_INPUT)}, /* spi1_cs0.gpio7_10 */
{SPI1_CS1, (M14 | PIN_INPUT)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */
+ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */
- {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */
- {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */
- {SPI2_CS0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_cs0.gpio7_17 */
- {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
- {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
- {UART1_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart1_rxd.uart1_rxd */
- {UART1_TXD, (M0 | PIN_OUTPUT_PULLDOWN)}, /* uart1_txd.uart1_txd */
+ {SPI2_D1, (M14 | PIN_INPUT_SLEW)}, /* spi2_d1.gpio7_15 */
+ {SPI2_D0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_d0.gpio7_16 */
+ {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */
+ {DCAN1_TX, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* dcan1_tx.dcan1_tx */
+ {DCAN1_RX, (M0 | PIN_INPUT | SLEWCONTROL)}, /* dcan1_rx.dcan1_rx */
+ {UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.uart1_rxd */
+ {UART1_TXD, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.uart1_txd */
{UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
{UART1_RTSN, (M14 | PIN_INPUT)}, /* uart1_rtsn.gpio7_25 */
{UART2_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_rxd.gpio7_26 */
{UART2_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.gpio7_27 */
{UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (M1 | PIN_OUTPUT_PULLDOWN)}, /* uart2_rtsn.uart3_txd */
+ {UART2_RTSN, (M1 | PIN_OUTPUT)}, /* uart2_rtsn.uart3_txd */
{I2C1_SDA, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_sda.i2c1_sda */
{I2C1_SCL, (M0 | PIN_INPUT_PULLUP)}, /* i2c1_scl.i2c1_scl */
{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
@@ -263,7 +223,7 @@
{ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
{RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
{TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
- {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */
+ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
{TDO, (M0 | PIN_OUTPUT)}, /* tdo.tdo */
{TCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* tclk.tclk */
{TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
@@ -275,11 +235,67 @@
};
const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1[] = {
- {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */
};
const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0[] = {
{VIN1A_CLK0, (M14 | PIN_INPUT)}, /* vin1a_clk0.gpio2_30 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
};
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
@@ -302,16 +318,16 @@
{GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
{GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
{GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
- {GPMC_A19, (M1 | PIN_INPUT)}, /* gpmc_a19.mmc2_dat4 */
- {GPMC_A20, (M1 | PIN_INPUT)}, /* gpmc_a20.mmc2_dat5 */
- {GPMC_A21, (M1 | PIN_INPUT)}, /* gpmc_a21.mmc2_dat6 */
- {GPMC_A22, (M1 | PIN_INPUT)}, /* gpmc_a22.mmc2_dat7 */
+ {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
+ {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
+ {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
+ {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
{GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
- {GPMC_A24, (M1 | PIN_INPUT)}, /* gpmc_a24.mmc2_dat0 */
- {GPMC_A25, (M1 | PIN_INPUT)}, /* gpmc_a25.mmc2_dat1 */
- {GPMC_A26, (M1 | PIN_INPUT)}, /* gpmc_a26.mmc2_dat2 */
- {GPMC_A27, (M1 | PIN_INPUT)}, /* gpmc_a27.mmc2_dat3 */
- {GPMC_CS1, (M1 | PIN_INPUT)}, /* gpmc_cs1.mmc2_cmd */
+ {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
+ {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
+ {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
+ {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
+ {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
{GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
{VIN1A_D5, (M14 | PIN_OUTPUT)}, /* vin1a_d5.gpio3_9 */
{VIN1A_D6, (M14 | PIN_OUTPUT)}, /* vin1a_d6.gpio3_10 */
@@ -351,37 +367,37 @@
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_de.vout1_de */
{VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
- {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */
- {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT)}, /* mdio_d.mdio_d */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE)}, /* vout1_d23.vout1_d23 */
+ {MDIO_MCLK, (M0 | PIN_INPUT_SLEW)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
{RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
{RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
{RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
@@ -394,8 +410,8 @@
{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_OUTPUT)}, /* usb2_drvvbus.usb2_drvvbus */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
{GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
{GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
{GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
@@ -404,50 +420,50 @@
{XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
{XREF_CLK3, (M9 | PIN_OUTPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
{MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
- {MCASP1_FSX, (M11 | PIN_INPUT)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
{MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
{MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
- {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */
- {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
{MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
{MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp1_axr4.gpio5_6 */
{MCASP1_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp1_axr5.gpio5_7 */
{MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
{MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr8.pr2_mii0_txen */
- {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr9.pr2_mii0_txd3 */
- {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr10.pr2_mii0_txd2 */
- {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr11.pr2_mii0_txd1 */
- {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP)}, /* mcasp1_axr12.pr2_mii0_txd0 */
- {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
- {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */
- {MCASP1_AXR15, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
{MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
- {MCASP2_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
- {MCASP2_AXR2, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
- {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
{MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
{MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
{MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
{MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
{MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
- {MCASP3_FSX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.pr2_mii0_col */
- {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */
- {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
{MCASP4_ACLKX, (M2 | PIN_INPUT)}, /* mcasp4_aclkx.spi3_sclk */
{MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
- {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP4_AXR1, (M2 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
{MCASP5_ACLKX, (M13 | PIN_OUTPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
{MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
- {MMC1_CMD, (M0 | PIN_INPUT)}, /* mmc1_cmd.mmc1_cmd */
- {MMC1_DAT0, (M0 | PIN_INPUT)}, /* mmc1_dat0.mmc1_dat0 */
- {MMC1_DAT1, (M0 | PIN_INPUT)}, /* mmc1_dat1.mmc1_dat1 */
- {MMC1_DAT2, (M0 | PIN_INPUT)}, /* mmc1_dat2.mmc1_dat2 */
- {MMC1_DAT3, (M0 | PIN_INPUT)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M14 | PIN_INPUT)}, /* mmc1_sdwp.gpio6_28 */
+ {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
+ {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
+ {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
+ {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
+ {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
+ {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
{GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
{GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
{MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
@@ -465,16 +481,16 @@
{SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
{SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
{SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT_PULLUP)}, /* spi1_cs3.hdmi1_cec */
+ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
{DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
- {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
- {SPI2_D1, (M0 | PIN_OUTPUT)}, /* spi2_d1.spi2_d1 */
- {SPI2_D0, (M0 | PIN_INPUT)}, /* spi2_d0.spi2_d0 */
- {SPI2_CS0, (M0 | PIN_OUTPUT)}, /* spi2_cs0.spi2_cs0 */
- {UART1_RXD, (M14 | PIN_OUTPUT)}, /* uart1_rxd.gpio7_22 */
- {UART1_TXD, (M14 | PIN_OUTPUT)}, /* uart1_txd.gpio7_23 */
+ {UART1_RXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
+ {UART1_TXD, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* uart1_txd.gpio7_23 */
{UART2_RXD, (M4 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
{UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
{UART2_CTSN, (M2 | PIN_INPUT)}, /* uart2_ctsn.uart3_rxd */
@@ -490,7 +506,7 @@
{ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
{RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
{TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
- {TDI, (M0 | PIN_INPUT_PULLUP)}, /* tdi.tdi */
+ {TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
{TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
{TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
{TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
@@ -498,29 +514,30 @@
{EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
{EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
{RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
+ {NMIN_DSP, (M0 | PIN_INPUT)}, /* nmin_dsp.nmin_dsp */
{RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
};
const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = {
- {GPMC_A0, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a0.vin1b_d0 */
- {GPMC_A1, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a1.vin1b_d1 */
- {GPMC_A2, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a2.vin1b_d2 */
- {GPMC_A3, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a3.vin1b_d3 */
- {GPMC_A4, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE11)}, /* gpmc_a4.vin1b_d4 */
- {GPMC_A5, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a5.vin1b_d5 */
- {GPMC_A6, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a6.vin1b_d6 */
- {GPMC_A7, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a7.vin1b_d7 */
- {GPMC_A8, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a8.vin1b_hsync1 */
- {GPMC_A9, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a9.vin1b_vsync1 */
- {GPMC_A10, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a10.vin1b_clk1 */
- {GPMC_A11, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE13)}, /* gpmc_a11.vin1b_de1 */
- {GPMC_A12, (M6 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE14)}, /* gpmc_a12.vin1b_fld1 */
- {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
- {GPMC_A14, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
- {GPMC_A15, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
- {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
- {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN) | MANUAL_MODE}, /* gpmc_a17.qspi1_d1 */
- {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
+ {GPMC_A0, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a0.vin1b_d0 */
+ {GPMC_A1, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a1.vin1b_d1 */
+ {GPMC_A2, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a2.vin1b_d2 */
+ {GPMC_A3, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a3.vin1b_d3 */
+ {GPMC_A4, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a4.vin1b_d4 */
+ {GPMC_A5, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a5.vin1b_d5 */
+ {GPMC_A6, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a6.vin1b_d6 */
+ {GPMC_A7, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a7.vin1b_d7 */
+ {GPMC_A8, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a8.vin1b_hsync1 */
+ {GPMC_A9, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a9.vin1b_vsync1 */
+ {GPMC_A10, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a10.vin1b_clk1 */
+ {GPMC_A11, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a11.vin1b_de1 */
+ {GPMC_A12, (M6 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a12.vin1b_fld1 */
+ {GPMC_A13, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
+ {GPMC_A14, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
+ {GPMC_A15, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
+ {GPMC_A16, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
+ {GPMC_A17, (M1 | PIN_INPUT | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
+ {GPMC_A18, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
{GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
{GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
{GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
@@ -531,234 +548,230 @@
{GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
{GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */
- {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */
- {GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
- {GPMC_CS3, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.gpio2_21 */
- {GPMC_CLK, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_clk.gpio2_22 */
- {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */
- {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */
- {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */
- {GPMC_BEN0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.gpio2_26 */
- {GPMC_BEN1, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_ben1.gpio2_27 */
- {GPMC_WAIT0, (M14 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
+ {GPMC_CS0, (M14 | PIN_OUTPUT)}, /* gpmc_cs0.gpio2_19 */
+ {GPMC_CS2, (M1 | PIN_OUTPUT | MANUAL_MODE)}, /* gpmc_cs2.qspi1_cs0 */
+ {GPMC_CS3, (M14 | PIN_OUTPUT)}, /* gpmc_cs3.gpio2_21 */
+ {GPMC_CLK, (M14 | PIN_INPUT)}, /* gpmc_clk.gpio2_22 */
+ {GPMC_ADVN_ALE, (M14 | PIN_OUTPUT)}, /* gpmc_advn_ale.gpio2_23 */
+ {GPMC_OEN_REN, (M14 | PIN_OUTPUT)}, /* gpmc_oen_ren.gpio2_24 */
+ {GPMC_WEN, (M14 | PIN_OUTPUT)}, /* gpmc_wen.gpio2_25 */
+ {GPMC_BEN0, (M14 | PIN_OUTPUT)}, /* gpmc_ben0.gpio2_26 */
+ {GPMC_BEN1, (M14 | PIN_OUTPUT)}, /* gpmc_ben1.gpio2_27 */
+ {GPMC_WAIT0, (M14 | PIN_OUTPUT | SLEWCONTROL)}, /* gpmc_wait0.gpio2_28 */
{VIN2A_CLK0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_clk0.gpio3_28 */
{VIN2A_DE0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_de0.gpio3_29 */
{VIN2A_FLD0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_fld0.gpio3_30 */
{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLUP)}, /* vin2a_hsync0.gpio3_31 */
- {VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_vsync0.gpio4_0 */
- {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */
- {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */
- {VIN2A_D2, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.eCAP1_in_PWM1_out */
- {VIN2A_D10, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
- {VIN2A_D11, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d11.pr1_mdio_data */
- {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
- {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
- {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
- {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
- {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
- {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
+ {VIN2A_VSYNC0, (M14 | PIN_OUTPUT)}, /* vin2a_vsync0.gpio4_0 */
+ {VIN2A_D0, (M11 | PIN_INPUT)}, /* vin2a_d0.pr1_uart0_rxd */
+ {VIN2A_D1, (M11 | PIN_OUTPUT)}, /* vin2a_d1.pr1_uart0_txd */
+ {VIN2A_D2, (M10 | PIN_OUTPUT)}, /* vin2a_d2.eCAP1_in_PWM1_out */
+ {VIN2A_D10, (M11 | PIN_OUTPUT_PULLDOWN)}, /* vin2a_d10.pr1_mdio_mdclk */
+ {VIN2A_D11, (M11 | PIN_INPUT)}, /* vin2a_d11.pr1_mdio_data */
+ {VIN2A_D12, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
+ {VIN2A_D13, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
+ {VIN2A_D14, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
+ {VIN2A_D15, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
+ {VIN2A_D16, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
+ {VIN2A_D17, (M3 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
{VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
- {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
+ {VIN2A_D19, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
{VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */
{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */
- {VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)}, /* vout1_fld.gpio4_21 */
- {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
- {MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mdio_d.mdio_d */
- {RMII_MHZ_50_CLK, (M13 | PIN_INPUT_PULLDOWN)}, /* RMII_MHZ_50_CLK.pr2_pru1_gpo2 */
- {UART3_RXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_rxd.gpio5_18 */
- {UART3_TXD, (M14 | PIN_INPUT_SLEW)}, /* uart3_txd.gpio5_19 */
- {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
- {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
- {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
- {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
- {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
- {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+ {VOUT1_FLD, (M14 | PIN_OUTPUT)}, /* vout1_fld.gpio4_21 */
+ {MDIO_MCLK, (M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mdio_mclk.mdio_mclk */
+ {MDIO_D, (M0 | PIN_INPUT | SLEWCONTROL)}, /* mdio_d.mdio_d */
+ {UART3_RXD, (M14 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* uart3_rxd.gpio5_18 */
+ {UART3_TXD, (M14 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* uart3_txd.gpio5_19 */
+ {RGMII0_TXC, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */
+ {RGMII0_TXCTL, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */
+ {RGMII0_TXD3, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+ {RGMII0_TXD2, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */
+ {RGMII0_TXD1, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+ {RGMII0_TXD0, (M0 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */
- {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},/* rgmii0_rxctl.rgmii0_rxctl */
- {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
- {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
- {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
- {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
- {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */
- {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */
- {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */
- {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */
- {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */
- {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */
- {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)}, /* xref_clk1.pr2_mii1_crs */
- {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */
- {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */
- {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
- {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */
- {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */
- {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */
- {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */
- {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
- {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */
- {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */
+ {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */
+ {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
+ {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
+ {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
+ {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
+ {USB1_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb1_drvvbus.usb1_drvvbus */
+ {USB2_DRVVBUS, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* usb2_drvvbus.usb2_drvvbus */
+ {GPIO6_14, (M0 | PIN_OUTPUT)}, /* gpio6_14.gpio6_14 */
+ {GPIO6_15, (M0 | PIN_OUTPUT)}, /* gpio6_15.gpio6_15 */
+ {GPIO6_16, (M0 | PIN_INPUT_PULLUP)}, /* gpio6_16.gpio6_16 */
+ {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */
+ {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */
+ {XREF_CLK2, (M14 | PIN_OUTPUT)}, /* xref_clk2.gpio6_19 */
+ {XREF_CLK3, (M7 | PIN_INPUT)}, /* xref_clk3.hdq0 */
+ {MCASP1_ACLKX, (M11 | PIN_OUTPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */
+ {MCASP1_FSX, (M11 | PIN_INPUT | SLEWCONTROL)}, /* mcasp1_fsx.pr2_mdio_data */
+ {MCASP1_ACLKR, (M14 | PIN_INPUT)}, /* mcasp1_aclkr.gpio5_0 */
+ {MCASP1_FSR, (M14 | PIN_INPUT)}, /* mcasp1_fsr.gpio5_1 */
+ {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */
+ {MCASP1_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.pr2_mii_mt0_clk */
+ {MCASP1_AXR2, (M14 | PIN_INPUT)}, /* mcasp1_axr2.gpio5_4 */
+ {MCASP1_AXR3, (M14 | PIN_INPUT)}, /* mcasp1_axr3.gpio5_5 */
{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */
- {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */
- {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */
- {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */
- {MCASP1_AXR8, (M11 | PIN_OUTPUT)}, /* mcasp1_axr8.pr2_mii0_txen */
- {MCASP1_AXR9, (M11 | PIN_OUTPUT)}, /* mcasp1_axr9.pr2_mii0_txd3 */
- {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */
- {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */
- {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */
- {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
- {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */
- {MCASP1_AXR15, (M11 | PIN_INPUT)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
- {MCASP2_ACLKX, (M11 | PIN_INPUT)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
- {MCASP2_FSX, (M11 | PIN_INPUT)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
- {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */
- {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */
- {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */
- {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */
- {MCASP2_AXR2, (M11 | PIN_INPUT)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
- {MCASP2_AXR3, (M11 | PIN_INPUT)}, /* mcasp2_axr3.pr2_mii0_rxlink */
- {MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */
- {MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */
- {MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */
- {MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */
- {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_aclkx.pr2_mii0_crs */
- {MCASP3_FSX, (M11 | PIN_INPUT)}, /* mcasp3_fsx.pr2_mii0_col */
- {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */
- {MCASP3_AXR1, (M11 | PIN_INPUT)}, /* mcasp3_axr1.pr2_mii1_rxlink */
- {MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */
- {MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */
- {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */
- {MCASP4_AXR1, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr1.spi3_cs0 */
- {MCASP5_ACLKX, (M13 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.pr2_pru1_gpo1 */
- {MCASP5_FSX, (M12 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
- {MCASP5_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.Driveroff */
- {MCASP5_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr1.Driveroff */
+ {MCASP1_AXR5, (M14 | PIN_INPUT)}, /* mcasp1_axr5.gpio5_7 */
+ {MCASP1_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp1_axr6.gpio5_8 */
+ {MCASP1_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp1_axr7.gpio5_9 */
+ {MCASP1_AXR8, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr8.pr2_mii0_txen */
+ {MCASP1_AXR9, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr9.pr2_mii0_txd3 */
+ {MCASP1_AXR10, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr10.pr2_mii0_txd2 */
+ {MCASP1_AXR11, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.pr2_mii0_txd1 */
+ {MCASP1_AXR12, (M11 | PIN_OUTPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr12.pr2_mii0_txd0 */
+ {MCASP1_AXR13, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr13.pr2_mii_mr0_clk */
+ {MCASP1_AXR14, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.pr2_mii0_rxdv */
+ {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */
+ {MCASP2_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */
+ {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */
+ {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */
+ {MCASP2_AXR3, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.pr2_mii0_rxlink */
+ {MCASP2_AXR4, (M14 | PIN_OUTPUT)}, /* mcasp2_axr4.gpio1_4 */
+ {MCASP2_AXR5, (M14 | PIN_OUTPUT)}, /* mcasp2_axr5.gpio6_7 */
+ {MCASP2_AXR6, (M14 | PIN_OUTPUT)}, /* mcasp2_axr6.gpio2_29 */
+ {MCASP2_AXR7, (M14 | PIN_OUTPUT)}, /* mcasp2_axr7.gpio1_5 */
+ {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */
+ {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */
+ {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */
+ {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */
+ {MCASP4_ACLKX, (M2 | PIN_OUTPUT)}, /* mcasp4_aclkx.spi3_sclk */
+ {MCASP4_FSX, (M2 | PIN_INPUT)}, /* mcasp4_fsx.spi3_d1 */
+ {MCASP4_AXR1, (M2 | PIN_OUTPUT_PULLUP)}, /* mcasp4_axr1.spi3_cs0 */
+ {MCASP5_AXR0, (M4 | PIN_INPUT)}, /* mcasp5_axr0.uart3_rxd */
+ {MCASP5_AXR1, (M4 | PIN_OUTPUT)}, /* mcasp5_axr1.uart3_txd */
{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */
{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */
{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */
{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */
{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */
{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */
- {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */
- {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */
- {GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.pr2_mii_mt1_clk */
- {GPIO6_11, (M11 | PIN_OUTPUT)}, /* gpio6_11.pr2_mii1_txen */
- {MMC3_CLK, (M11 | PIN_OUTPUT)}, /* mmc3_clk.pr2_mii1_txd3 */
- {MMC3_CMD, (M11 | PIN_OUTPUT)}, /* mmc3_cmd.pr2_mii1_txd2 */
- {MMC3_DAT0, (M11 | PIN_OUTPUT)}, /* mmc3_dat0.pr2_mii1_txd1 */
- {MMC3_DAT1, (M11 | PIN_OUTPUT)}, /* mmc3_dat1.pr2_mii1_txd0 */
- {MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat2.pr2_mii_mr1_clk */
+ {MMC1_SDCD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdcd.gpio6_27 */
+ {MMC1_SDWP, (M14 | PIN_INPUT | SLEWCONTROL)}, /* mmc1_sdwp.gpio6_28 */
+ {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */
+ {GPIO6_11, (M11 | PIN_OUTPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */
+ {MMC3_CLK, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */
+ {MMC3_CMD, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */
+ {MMC3_DAT0, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */
+ {MMC3_DAT1, (M11 | PIN_OUTPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */
+ {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */
{MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */
- {MMC3_DAT4, (M11 | PIN_INPUT)}, /* mmc3_dat4.pr2_mii1_rxd3 */
- {MMC3_DAT5, (M11 | PIN_INPUT)}, /* mmc3_dat5.pr2_mii1_rxd2 */
- {MMC3_DAT6, (M11 | PIN_INPUT)}, /* mmc3_dat6.pr2_mii1_rxd1 */
- {MMC3_DAT7, (M11 | PIN_INPUT)}, /* mmc3_dat7.pr2_mii1_rxd0 */
- {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */
- {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */
- {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */
- {SPI1_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs0.gpio7_10 */
- {SPI1_CS1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs1.gpio7_11 */
- {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */
- {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
- {SPI2_SCLK, (M0 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.spi2_sclk */
- {SPI2_D1, (M0 | PIN_INPUT_SLEW)}, /* spi2_d1.spi2_d1 */
- {SPI2_D0, (M0 | PIN_INPUT_SLEW)}, /* spi2_d0.spi2_d0 */
- {SPI2_CS0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
+ {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */
+ {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */
+ {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */
+ {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */
+ {SPI1_SCLK, (M14 | PIN_OUTPUT)}, /* spi1_sclk.gpio7_7 */
+ {SPI1_D1, (M14 | PIN_OUTPUT)}, /* spi1_d1.gpio7_8 */
+ {SPI1_D0, (M14 | PIN_OUTPUT)}, /* spi1_d0.gpio7_9 */
+ {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */
+ {SPI1_CS1, (M14 | PIN_OUTPUT)}, /* spi1_cs1.gpio7_11 */
+ {SPI1_CS2, (M14 | PIN_INPUT_SLEW)}, /* spi1_cs2.gpio7_12 */
+ {SPI1_CS3, (M6 | PIN_INPUT | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */
+ {SPI2_SCLK, (M0 | PIN_INPUT)}, /* spi2_sclk.spi2_sclk */
+ {SPI2_D1, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d1.spi2_d1 */
+ {SPI2_D0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_d0.spi2_d0 */
+ {SPI2_CS0, (M0 | PIN_INPUT | SLEWCONTROL)}, /* spi2_cs0.spi2_cs0 */
{DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */
{DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */
- {UART1_RXD, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
- {UART1_CTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.gpio7_24 */
- {UART1_RTSN, (M14 | PIN_INPUT_PULLDOWN)}, /* uart1_rtsn.gpio7_25 */
- {UART2_RXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_rxd.uart2_rxd */
- {UART2_TXD, (M0 | PIN_INPUT_PULLUP)}, /* uart2_txd.uart2_txd */
- {UART2_CTSN, (M2 | PIN_INPUT_PULLUP)}, /* uart2_ctsn.uart3_rxd */
- {UART2_RTSN, (M1 | PIN_INPUT_PULLUP)}, /* uart2_rtsn.uart3_txd */
- {I2C2_SDA, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_sda.hdmi1_ddc_scl */
- {I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
- {WAKEUP0, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup0.Wakeup0 */
- {WAKEUP3, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup3.Wakeup3 */
- {ON_OFF, (M0 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */
- {RTC_PORZ, (M0 | PIN_OUTPUT)}, /* rtc_porz.rtc_porz */
+ {UART1_RXD, (M14 | PIN_INPUT | SLEWCONTROL)}, /* uart1_rxd.gpio7_22 */
+ {UART1_CTSN, (M14 | PIN_OUTPUT)}, /* uart1_ctsn.gpio7_24 */
+ {UART1_RTSN, (M14 | PIN_OUTPUT)}, /* uart1_rtsn.gpio7_25 */
+ {I2C1_SDA, (M0 | PIN_INPUT)}, /* i2c1_sda.i2c1_sda */
+ {I2C1_SCL, (M0 | PIN_INPUT)}, /* i2c1_scl.i2c1_scl */
+ {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */
+ {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */
+ {WAKEUP0, (M0 | PIN_INPUT)}, /* Wakeup0.Wakeup0 */
+ {WAKEUP3, (M0 | PIN_INPUT)}, /* Wakeup3.Wakeup3 */
+ {ON_OFF, (M0 | PIN_OUTPUT)}, /* on_off.on_off */
+ {RTC_PORZ, (M0 | PIN_INPUT)}, /* rtc_porz.rtc_porz */
{TMS, (M0 | PIN_INPUT_PULLUP)}, /* tms.tms */
{TDI, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* tdi.tdi */
- {TDO, (M0 | PIN_INPUT_PULLUP)}, /* tdo.tdo */
+ {TDO, (M0 | PIN_OUTPUT_PULLUP)}, /* tdo.tdo */
{TCLK, (M0 | PIN_INPUT_PULLUP)}, /* tclk.tclk */
- {TRSTN, (M0 | PIN_INPUT_PULLDOWN)}, /* trstn.trstn */
- {RTCK, (M0 | PIN_INPUT)}, /* rtck.rtck */
- {EMU0, (M0 | PIN_INPUT_PULLUP)}, /* emu0.emu0 */
- {EMU1, (M0 | PIN_INPUT_PULLUP)}, /* emu1.emu1 */
- {RESETN, (M0 | PIN_OUTPUT_PULLUP)}, /* resetn.resetn */
- {RSTOUTN, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rstoutn.rstoutn */
+ {TRSTN, (M0 | PIN_INPUT)}, /* trstn.trstn */
+ {RTCK, (M0 | PIN_OUTPUT_PULLUP)}, /* rtck.rtck */
+ {EMU0, (M0 | PIN_INPUT)}, /* emu0.emu0 */
+ {EMU1, (M0 | PIN_INPUT)}, /* emu1.emu1 */
+ {RESETN, (M0 | PIN_INPUT)}, /* resetn.resetn */
+ {RSTOUTN, (M0 | PIN_OUTPUT)}, /* rstoutn.rstoutn */
};
const struct pad_conf_entry core_padconf_array_icss1eth_am571x_idk[] = {
/* PR1 MII0 */
- {VOUT1_D8, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.pr1_mii_mt0_clk */
- {VOUT1_D9, (M13 | PIN_OUTPUT)}, /* vout1_d9.pr1_mii0_txd3 */
- {VOUT1_D10, (M13 | PIN_OUTPUT)}, /* vout1_d10.pr1_mii0_txd2 */
- {VOUT1_D11, (M13 | PIN_OUTPUT)}, /* vout1_d11.pr1_mii0_txen */
- {VOUT1_D12, (M13 | PIN_OUTPUT)}, /* vout1_d12.pr1_mii0_txd1 */
- {VOUT1_D13, (M13 | PIN_OUTPUT)}, /* vout1_d13.pr1_mii0_txd0 */
- {VOUT1_D14, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.pr1_mii_mr0_clk */
+ {VOUT1_D8, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d8.pr1_mii_mt0_clk */
+ {VOUT1_D9, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d9.pr1_mii0_txd3 */
+ {VOUT1_D10, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d10.pr1_mii0_txd2 */
+ {VOUT1_D11, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d11.pr1_mii0_txen */
+ {VOUT1_D12, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d12.pr1_mii0_txd1 */
+ {VOUT1_D13, (M13 | PIN_OUTPUT_PULLUP)}, /* vout1_d13.pr1_mii0_txd0 */
+ {VOUT1_D14, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d14.pr1_mii_mr0_clk */
{VOUT1_D15, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.pr1_mii0_rxdv */
- {VOUT1_D16, (M12 | PIN_INPUT)}, /* vout1_d16.pr1_mii0_rxd3 */
- {VOUT1_D17, (M12 | PIN_INPUT)}, /* vout1_d17.pr1_mii0_rxd2 */
- {VOUT1_D18, (M12 | PIN_INPUT)}, /* vout1_d18.pr1_mii0_rxd1 */
- {VOUT1_D19, (M12 | PIN_INPUT)}, /* vout1_d19.pr1_mii0_rxd0 */
+ {VOUT1_D16, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.pr1_mii0_rxd3 */
+ {VOUT1_D17, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.pr1_mii0_rxd2 */
+ {VOUT1_D18, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.pr1_mii0_rxd1 */
+ {VOUT1_D19, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.pr1_mii0_rxd0 */
{VOUT1_D20, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d20.pr1_mii0_rxer */
- {VOUT1_D21, (M12 | PIN_INPUT)}, /* vout1_d21.pr1_mii0_rxlink */
- {VOUT1_D22, (M12 | PIN_INPUT)}, /* vout1_d22.pr1_mii0_col */
- {VOUT1_D23, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d23.pr1_mii0_crs */
+ {VOUT1_D21, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.pr1_mii0_rxlink */
+ {VOUT1_D22, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.pr1_mii0_col */
+ {VOUT1_D23, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.pr1_mii0_crs */
/* PR1 MII1 */
- {VIN2A_D3, (M12 | PIN_INPUT)}, /* vin2a_d3.pr1_mi1_col */
- {VIN2A_D4, (M13 | PIN_OUTPUT)}, /* vin2a_d4.pr1_mii1_txd1 */
- {VIN2A_D5, (M13 | PIN_OUTPUT)}, /* vin2a_d5.pr1_mii1_txd0 */
- {VIN2A_D6, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.pr1_mii_mt1_clk */
- {VIN2A_D7, (M11 | PIN_OUTPUT)}, /* vin2a_d7.pr1_mii1_txen */
- {VIN2A_D8, (M11 | PIN_OUTPUT)}, /* vin2a_d8.pr1_mii1_txd3 */
- {VIN2A_D9, (M11 | PIN_OUTPUT)}, /* vin2a_d9.pr1_mii1_txd2 */
+ {VIN2A_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.pr1_mii1_col */
+ {VIN2A_D4, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d4.pr1_mii1_txd1 */
+ {VIN2A_D5, (M13 | PIN_OUTPUT_PULLUP)}, /* vin2a_d5.pr1_mii1_txd0 */
+ {VIN2A_D6, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_d6.pr1_mii_mt1_clk */
+ {VIN2A_D7, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d7.pr1_mii1_txen */
+ {VIN2A_D8, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d8.pr1_mii1_txd3 */
+ {VIN2A_D9, (M11 | PIN_OUTPUT_PULLUP)}, /* vin2a_d9.pr1_mii1_txd2 */
{VOUT1_VSYNC, (M12 | PIN_INPUT_PULLUP)}, /* vout1_vsync.pr1_mii1_rxer */
- {VOUT1_D0, (M12 | PIN_INPUT)}, /* vout1_d0.pr1_mii1_rxlink */
- {VOUT1_D1, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d1.pr1_mii1_crs */
- {VOUT1_D2, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.pr1_mii_mr1_clk */
+ {VOUT1_D0, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d0.pr1_mii1_rxlink */
+ {VOUT1_D1, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.pr1_mii1_crs */
+ {VOUT1_D2, (M12 | PIN_INPUT_PULLUP)}, /* vout1_d2.pr1_mii_mr1_clk */
{VOUT1_D3, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.pr1_mii1_rxdv */
- {VOUT1_D4, (M12 | PIN_INPUT)}, /* vout1_d4.pr1_mii1_rxd3 */
- {VOUT1_D5, (M12 | PIN_INPUT)}, /* vout1_d5.pr1_mii1_rxd2 */
- {VOUT1_D6, (M12 | PIN_INPUT)}, /* vout1_d6.pr1_mii1_rxd1 */
- {VOUT1_D7, (M12 | PIN_INPUT)}, /* vout1_d7.pr1_mii1_rxd0 */
+ {VOUT1_D4, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.pr1_mii1_rxd3 */
+ {VOUT1_D5, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.pr1_mii1_rxd2 */
+ {VOUT1_D6, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.pr1_mii1_rxd1 */
+ {VOUT1_D7, (M12 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.pr1_mii1_rxd0 */
};
const struct pad_conf_entry core_padconf_array_vout_am571x_idk[] = {
- {VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_clk.vout1_clk */
- {VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_de.vout1_de */
- {VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_hsync.vout1_hsync */
- {VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_vsync.vout1_vsync */
- {VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d0.vout1_d0 */
- {VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d1.vout1_d1 */
- {VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d2.vout1_d2 */
- {VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d3.vout1_d3 */
- {VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d4.vout1_d4 */
- {VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d5.vout1_d5 */
- {VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d6.vout1_d6 */
- {VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d7.vout1_d7 */
- {VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d8.vout1_d8 */
- {VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d9.vout1_d9 */
- {VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d10.vout1_d10 */
- {VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d11.vout1_d11 */
- {VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d12.vout1_d12 */
- {VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d13.vout1_d13 */
- {VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d14.vout1_d14 */
- {VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d15.vout1_d15 */
- {VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d16.vout1_d16 */
- {VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d17.vout1_d17 */
- {VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d18.vout1_d18 */
- {VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d19.vout1_d19 */
- {VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d20.vout1_d20 */
- {VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d21.vout1_d21 */
- {VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d22.vout1_d22 */
- {VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN)}, /* vout1_d23.vout1_d23 */
+ {VOUT1_CLK, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_clk.vout1_clk */
+ {VOUT1_DE, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_de.vout1_de */
+ {VOUT1_HSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_hsync.vout1_hsync */
+ {VOUT1_VSYNC, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_vsync.vout1_vsync */
+ {VOUT1_D0, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d0.vout1_d0 */
+ {VOUT1_D1, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d1.vout1_d1 */
+ {VOUT1_D2, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d2.vout1_d2 */
+ {VOUT1_D3, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d3.vout1_d3 */
+ {VOUT1_D4, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d4.vout1_d4 */
+ {VOUT1_D5, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d5.vout1_d5 */
+ {VOUT1_D6, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d6.vout1_d6 */
+ {VOUT1_D7, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d7.vout1_d7 */
+ {VOUT1_D8, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d8.vout1_d8 */
+ {VOUT1_D9, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d9.vout1_d9 */
+ {VOUT1_D10, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d10.vout1_d10 */
+ {VOUT1_D11, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d11.vout1_d11 */
+ {VOUT1_D12, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d12.vout1_d12 */
+ {VOUT1_D13, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d13.vout1_d13 */
+ {VOUT1_D14, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d14.vout1_d14 */
+ {VOUT1_D15, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d15.vout1_d15 */
+ {VOUT1_D16, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d16.vout1_d16 */
+ {VOUT1_D17, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d17.vout1_d17 */
+ {VOUT1_D18, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d18.vout1_d18 */
+ {VOUT1_D19, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d19.vout1_d19 */
+ {VOUT1_D20, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d20.vout1_d20 */
+ {VOUT1_D21, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d21.vout1_d21 */
+ {VOUT1_D22, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d22.vout1_d22 */
+ {VOUT1_D23, (M0 | PIN_OUTPUT | SLEWCONTROL)}, /* vout1_d23.vout1_d23 */
+
+ {MCASP5_ACLKX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_aclkx.pr2_pru1_gpi1 */
+ {MCASP5_FSX, (M12 | PIN_INPUT | MANUAL_MODE)}, /* mcasp5_fsx.pr2_pru1_gpi2 */
+ {UART2_RXD, (M0 | PIN_INPUT)}, /* uart2_rxd.uart2_rxd */
+ {UART2_TXD, (M0 | PIN_OUTPUT)}, /* uart2_txd.uart2_txd */
+ {VIN2A_D5, (M13 | PIN_OUTPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d5.pr1_pru1_gpo2 */
};
const struct pad_conf_entry early_padconf[] = {
@@ -798,6 +811,36 @@
{0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */
{0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */
{0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */
+ {0x0378, 0, 0}, /* CFG_GPMC_CS3_IN */
+ {0x0678, 406, 0}, /* CFG_MMC3_CLK_IN */
+ {0x0680, 659, 0}, /* CFG_MMC3_CLK_OUT */
+ {0x0684, 0, 0}, /* CFG_MMC3_CMD_IN */
+ {0x0688, 0, 0}, /* CFG_MMC3_CMD_OEN */
+ {0x068C, 0, 0}, /* CFG_MMC3_CMD_OUT */
+ {0x0690, 130, 0}, /* CFG_MMC3_DAT0_IN */
+ {0x0694, 0, 0}, /* CFG_MMC3_DAT0_OEN */
+ {0x0698, 0, 0}, /* CFG_MMC3_DAT0_OUT */
+ {0x069C, 169, 0}, /* CFG_MMC3_DAT1_IN */
+ {0x06A0, 0, 0}, /* CFG_MMC3_DAT1_OEN */
+ {0x06A4, 0, 0}, /* CFG_MMC3_DAT1_OUT */
+ {0x06A8, 0, 0}, /* CFG_MMC3_DAT2_IN */
+ {0x06AC, 0, 0}, /* CFG_MMC3_DAT2_OEN */
+ {0x06B0, 0, 0}, /* CFG_MMC3_DAT2_OUT */
+ {0x06B4, 457, 0}, /* CFG_MMC3_DAT3_IN */
+ {0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
+ {0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
+ {0x06C0, 702, 0}, /* CFG_MMC3_DAT4_IN */
+ {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
+ {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
+ {0x06CC, 738, 0}, /* CFG_MMC3_DAT5_IN */
+ {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
+ {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
+ {0x06D8, 856, 0}, /* CFG_MMC3_DAT6_IN */
+ {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
+ {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
+ {0x06E4, 610, 0}, /* CFG_MMC3_DAT7_IN */
+ {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
+ {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
{0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */
{0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */
{0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */
@@ -815,7 +858,7 @@
{0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */
{0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */
{0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
{0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */
{0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */
{0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */
@@ -871,6 +914,18 @@
{0x06B4, 474, 0}, /* CFG_MMC3_DAT3_IN */
{0x06B8, 0, 0}, /* CFG_MMC3_DAT3_OEN */
{0x06BC, 0, 0}, /* CFG_MMC3_DAT3_OUT */
+ {0x06C0, 792, 0}, /* CFG_MMC3_DAT4_IN */
+ {0x06C4, 0, 0}, /* CFG_MMC3_DAT4_OEN */
+ {0x06C8, 0, 0}, /* CFG_MMC3_DAT4_OUT */
+ {0x06CC, 782, 0}, /* CFG_MMC3_DAT5_IN */
+ {0x06D0, 0, 0}, /* CFG_MMC3_DAT5_OEN */
+ {0x06D4, 0, 0}, /* CFG_MMC3_DAT5_OUT */
+ {0x06D8, 942, 0}, /* CFG_MMC3_DAT6_IN */
+ {0x06DC, 0, 0}, /* CFG_MMC3_DAT6_OEN */
+ {0x06E0, 0, 0}, /* CFG_MMC3_DAT6_OUT */
+ {0x06E4, 636, 0}, /* CFG_MMC3_DAT7_IN */
+ {0x06E8, 0, 0}, /* CFG_MMC3_DAT7_OEN */
+ {0x06EC, 0, 0}, /* CFG_MMC3_DAT7_OUT */
{0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
{0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
{0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
@@ -895,6 +950,34 @@
{0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
{0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
{0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
+ {0x0B9C, 0, 706}, /* CFG_VOUT1_CLK_OUT */
+ {0x0BA8, 2313, 0}, /* CFG_VOUT1_D0_OUT */
+ {0x0BB4, 2199, 0}, /* CFG_VOUT1_D10_OUT */
+ {0x0BC0, 2266, 0}, /* CFG_VOUT1_D11_OUT */
+ {0x0BCC, 3159, 0}, /* CFG_VOUT1_D12_OUT */
+ {0x0BD8, 2100, 0}, /* CFG_VOUT1_D13_OUT */
+ {0x0BE4, 2229, 0}, /* CFG_VOUT1_D14_OUT */
+ {0x0BF0, 2202, 0}, /* CFG_VOUT1_D15_OUT */
+ {0x0BFC, 2084, 0}, /* CFG_VOUT1_D16_OUT */
+ {0x0C08, 2195, 0}, /* CFG_VOUT1_D17_OUT */
+ {0x0C14, 2342, 0}, /* CFG_VOUT1_D18_OUT */
+ {0x0C20, 2463, 0}, /* CFG_VOUT1_D19_OUT */
+ {0x0C2C, 2439, 0}, /* CFG_VOUT1_D1_OUT */
+ {0x0C38, 2304, 0}, /* CFG_VOUT1_D20_OUT */
+ {0x0C44, 2103, 0}, /* CFG_VOUT1_D21_OUT */
+ {0x0C50, 2145, 0}, /* CFG_VOUT1_D22_OUT */
+ {0x0C5C, 1932, 0}, /* CFG_VOUT1_D23_OUT */
+ {0x0C68, 2200, 0}, /* CFG_VOUT1_D2_OUT */
+ {0x0C74, 2355, 0}, /* CFG_VOUT1_D3_OUT */
+ {0x0C80, 3215, 0}, /* CFG_VOUT1_D4_OUT */
+ {0x0C8C, 2314, 0}, /* CFG_VOUT1_D5_OUT */
+ {0x0C98, 2238, 0}, /* CFG_VOUT1_D6_OUT */
+ {0x0CA4, 2381, 0}, /* CFG_VOUT1_D7_OUT */
+ {0x0CB0, 2138, 0}, /* CFG_VOUT1_D8_OUT */
+ {0x0CBC, 2383, 0}, /* CFG_VOUT1_D9_OUT */
+ {0x0CC8, 1984, 0}, /* CFG_VOUT1_DE_OUT */
+ {0x0CE0, 1947, 0}, /* CFG_VOUT1_HSYNC_OUT */
+ {0x0CEC, 2739, 0}, /* CFG_VOUT1_VSYNC_OUT */
};
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk[] = {
@@ -921,68 +1004,113 @@
{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
{0x0590, 1000, 4200}, /* CFG_MCASP5_ACLKX_OUT */
{0x05AC, 800, 3800}, /* CFG_MCASP5_FSX_IN */
- {0x06F0, 471, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 30, 1919}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 74, 1688}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 94, 1697}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 0, 1703}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 70, 1804}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 90, 70}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 70, 70}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 180, 70}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 35, 70}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 0}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 180, 70}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A70, 65, 70}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 125, 70}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 0, 70}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 70}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 65, 70}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 612, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 4, 927}, /* CFG_VIN2A_D19_IN */
- {0x0AD4, 136, 1340}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 130, 1450}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 144, 1269}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1330}, /* CFG_VIN2A_D23_IN */
+ {0x06F0, 260, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 0, 1412}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 123, 1047}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 139, 1081}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 195, 1100}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 239, 1216}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 89, 0}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 15, 125}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 339, 162}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 146, 94}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 27}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 291, 205}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 219, 101}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 92, 58}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 135, 100}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 154, 101}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 78, 27}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 411, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 0, 382}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 320, 750}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 192, 836}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 294, 669}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 50, 700}, /* CFG_VIN2A_D23_IN */
{0x0B30, 0, 0}, /* CFG_VIN2A_D5_OUT */
+ {0x0B9C, 1126, 751}, /* CFG_VOUT1_CLK_OUT */
+ {0x0BA8, 395, 0}, /* CFG_VOUT1_D0_OUT */
+ {0x0BB4, 282, 0}, /* CFG_VOUT1_D10_OUT */
+ {0x0BC0, 348, 0}, /* CFG_VOUT1_D11_OUT */
+ {0x0BCC, 1240, 0}, /* CFG_VOUT1_D12_OUT */
+ {0x0BD8, 182, 0}, /* CFG_VOUT1_D13_OUT */
+ {0x0BE4, 311, 0}, /* CFG_VOUT1_D14_OUT */
+ {0x0BF0, 285, 0}, /* CFG_VOUT1_D15_OUT */
+ {0x0BFC, 166, 0}, /* CFG_VOUT1_D16_OUT */
+ {0x0C08, 278, 0}, /* CFG_VOUT1_D17_OUT */
+ {0x0C14, 425, 0}, /* CFG_VOUT1_D18_OUT */
+ {0x0C20, 516, 0}, /* CFG_VOUT1_D19_OUT */
+ {0x0C2C, 521, 0}, /* CFG_VOUT1_D1_OUT */
+ {0x0C38, 386, 0}, /* CFG_VOUT1_D20_OUT */
+ {0x0C44, 111, 0}, /* CFG_VOUT1_D21_OUT */
+ {0x0C50, 227, 0}, /* CFG_VOUT1_D22_OUT */
+ {0x0C5C, 0, 0}, /* CFG_VOUT1_D23_OUT */
+ {0x0C68, 282, 0}, /* CFG_VOUT1_D2_OUT */
+ {0x0C74, 438, 0}, /* CFG_VOUT1_D3_OUT */
+ {0x0C80, 1298, 0}, /* CFG_VOUT1_D4_OUT */
+ {0x0C8C, 397, 0}, /* CFG_VOUT1_D5_OUT */
+ {0x0C98, 321, 0}, /* CFG_VOUT1_D6_OUT */
+ {0x0CA4, 155, 309}, /* CFG_VOUT1_D7_OUT */
+ {0x0CB0, 212, 0}, /* CFG_VOUT1_D8_OUT */
+ {0x0CBC, 466, 0}, /* CFG_VOUT1_D9_OUT */
+ {0x0CC8, 0, 0}, /* CFG_VOUT1_DE_OUT */
+ {0x0CE0, 0, 0}, /* CFG_VOUT1_HSYNC_OUT */
+ {0x0CEC, 139, 701}, /* CFG_VOUT1_VSYNC_OUT */
};
const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] = {
- {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
- {0x0150, 2062, 2277}, /* CFG_GPMC_A14_IN */
- {0x015C, 1960, 2289}, /* CFG_GPMC_A15_IN */
- {0x0168, 2058, 2386}, /* CFG_GPMC_A16_IN */
- {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
- {0x0174, 2062, 2350}, /* CFG_GPMC_A17_IN */
- {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
- {0x0374, 121, 0}, /* CFG_GPMC_CS2_OUT */
- {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
- {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
- {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
- {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
- {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
- {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
- {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
- {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
- {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
- {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
- {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
- {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
- {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
- {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
- {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
- {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
- {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
- {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
- {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
- {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
- {0x0AC8, 2229, 10}, /* CFG_VIN2A_D1_IN */
- {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
- {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
- {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
- {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
+ {0x0114, 1873, 702}, /* CFG_GPMC_A0_IN */
+ {0x0120, 0, 0}, /* CFG_GPMC_A10_IN */
+ {0x012C, 1851, 1011}, /* CFG_GPMC_A11_IN */
+ {0x0138, 2009, 601}, /* CFG_GPMC_A12_IN */
+ {0x0144, 0, 0}, /* CFG_GPMC_A13_IN */
+ {0x0150, 2247, 1186}, /* CFG_GPMC_A14_IN */
+ {0x015C, 2176, 1197}, /* CFG_GPMC_A15_IN */
+ {0x0168, 2229, 1268}, /* CFG_GPMC_A16_IN */
+ {0x0170, 0, 0}, /* CFG_GPMC_A16_OUT */
+ {0x0174, 2251, 1217}, /* CFG_GPMC_A17_IN */
+ {0x0188, 0, 0}, /* CFG_GPMC_A18_OUT */
+ {0x0198, 1629, 772}, /* CFG_GPMC_A1_IN */
+ {0x0204, 1734, 898}, /* CFG_GPMC_A2_IN */
+ {0x0210, 1757, 1076}, /* CFG_GPMC_A3_IN */
+ {0x021C, 1794, 893}, /* CFG_GPMC_A4_IN */
+ {0x0228, 1726, 853}, /* CFG_GPMC_A5_IN */
+ {0x0234, 1792, 612}, /* CFG_GPMC_A6_IN */
+ {0x0240, 2117, 610}, /* CFG_GPMC_A7_IN */
+ {0x024C, 1758, 653}, /* CFG_GPMC_A8_IN */
+ {0x0258, 1705, 899}, /* CFG_GPMC_A9_IN */
+ {0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */
+ {0x06F0, 413, 0}, /* CFG_RGMII0_RXC_IN */
+ {0x06FC, 27, 2296}, /* CFG_RGMII0_RXCTL_IN */
+ {0x0708, 3, 1721}, /* CFG_RGMII0_RXD0_IN */
+ {0x0714, 134, 1786}, /* CFG_RGMII0_RXD1_IN */
+ {0x0720, 40, 1966}, /* CFG_RGMII0_RXD2_IN */
+ {0x072C, 0, 2057}, /* CFG_RGMII0_RXD3_IN */
+ {0x0740, 0, 60}, /* CFG_RGMII0_TXC_OUT */
+ {0x074C, 0, 60}, /* CFG_RGMII0_TXCTL_OUT */
+ {0x0758, 0, 60}, /* CFG_RGMII0_TXD0_OUT */
+ {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */
+ {0x0770, 0, 60}, /* CFG_RGMII0_TXD2_OUT */
+ {0x077C, 0, 120}, /* CFG_RGMII0_TXD3_OUT */
+ {0x0A70, 0, 0}, /* CFG_VIN2A_D12_OUT */
+ {0x0A7C, 170, 0}, /* CFG_VIN2A_D13_OUT */
+ {0x0A88, 150, 0}, /* CFG_VIN2A_D14_OUT */
+ {0x0A94, 0, 0}, /* CFG_VIN2A_D15_OUT */
+ {0x0AA0, 60, 0}, /* CFG_VIN2A_D16_OUT */
+ {0x0AAC, 60, 0}, /* CFG_VIN2A_D17_OUT */
+ {0x0AB0, 530, 0}, /* CFG_VIN2A_D18_IN */
+ {0x0ABC, 71, 1099}, /* CFG_VIN2A_D19_IN */
+ {0x0AD4, 142, 1337}, /* CFG_VIN2A_D20_IN */
+ {0x0AE0, 114, 1517}, /* CFG_VIN2A_D21_IN */
+ {0x0AEC, 171, 1331}, /* CFG_VIN2A_D22_IN */
+ {0x0AF8, 0, 1328}, /* CFG_VIN2A_D23_IN */
};
+const struct iodelay_cfg_entry iodelay_cfg_array_am571x_idk_4port[] = {
+ {0x0588, 2100, 1959}, /* CFG_MCASP5_ACLKX_IN */
+ {0x05AC, 2100, 1780}, /* CFG_MCASP5_FSX_IN */
+ {0x0B30, 0, 400}, /* CFG_VIN2A_D5_OUT */
+};
#endif
#endif /* _MUX_DATA_BEAGLE_X15_H_ */
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 270cff6..412bf24 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -266,7 +266,9 @@
Extract a part of a multi-image.
config CMD_POWEROFF
- bool
+ bool "poweroff"
+ help
+ Poweroff/Shutdown the system
endmenu
diff --git a/cmd/jffs2.c b/cmd/jffs2.c
index f00d53a..9be198e 100644
--- a/cmd/jffs2.c
+++ b/cmd/jffs2.c
@@ -606,7 +606,7 @@
" with offset 'off'"
);
U_BOOT_CMD(
- ls, 2, 1, do_jffs2_ls,
+ fsls, 2, 1, do_jffs2_ls,
"list files in a directory (default /)",
"[ directory ]"
);
diff --git a/common/edid.c b/common/edid.c
index 19410aa..854d40c 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -295,7 +295,7 @@
h_total = h_active + h_blanking;
v_total = v_active + v_blanking;
- if (v_total * h_total)
+ if (v_total > 0 && h_total > 0)
vfreq = pixclock / (v_total * h_total);
else
vfreq = 1; /* Error case */
diff --git a/common/env_mmc.c b/common/env_mmc.c
index 404de85..88b043e 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -121,7 +121,12 @@
if (!mmc)
return "!No MMC card found";
-#ifndef CONFIG_BLK
+#ifdef CONFIG_BLK
+ struct udevice *dev;
+
+ if (blk_get_from_parent(mmc->dev, &dev))
+ return "!No block device";
+#else
if (mmc_init(mmc))
return "!MMC init failed";
#endif
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 732690c..4de8139 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -437,6 +437,15 @@
a memory-mapped device makes it very easy to access. Loading from
NOR is typically achieved with just a memcpy().
+config SPL_XIP_SUPPORT
+ bool "Support XIP"
+ depends on SPL
+ help
+ Enable support for execute in place of U-Boot or kernel image. There
+ is no need to copy image from flash to ram if flash supports execute
+ in place. Its very useful in systems having enough flash but not
+ enough ram to load the image.
+
config SPL_ONENAND_SUPPORT
bool "Support OneNAND flash"
help
diff --git a/common/spl/Makefile b/common/spl/Makefile
index b3b34d6..47a64dd 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
+obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
ifndef CONFIG_SPL_UBI
obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
diff --git a/common/spl/spl.c b/common/spl/spl.c
index f493a3a..7f3fd92 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -121,9 +121,6 @@
{
spl_image->size = CONFIG_SYS_MONITOR_LEN;
spl_image->entry_point = CONFIG_SYS_UBOOT_START;
-#ifdef CONFIG_CPU_V7M
- spl_image->entry_point |= 0x1;
-#endif
spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
@@ -405,6 +402,9 @@
hang();
}
+#ifdef CONFIG_CPU_V7M
+ spl_image.entry_point |= 0x1;
+#endif
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to U-Boot\n");
diff --git a/common/spl/spl_xip.c b/common/spl/spl_xip.c
new file mode 100644
index 0000000..18c7d11
--- /dev/null
+++ b/common/spl/spl_xip.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2017 Vikas Manocha <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+static int spl_xip(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+#ifdef CONFIG_SPL_OS_BOOT
+ if (!spl_start_uboot()) {
+ spl_image->arg = (void *)CONFIG_SYS_FDT_BASE;
+ spl_image->name = "Linux";
+ spl_image->os = IH_OS_LINUX;
+ spl_image->load_addr = CONFIG_SYS_LOAD_ADDR;
+ spl_image->entry_point = CONFIG_SYS_LOAD_ADDR;
+ debug("spl: payload xipImage, load addr: 0x%lx\n",
+ spl_image->load_addr);
+ return 0;
+ }
+#endif
+ return(spl_parse_image_header(spl_image, (const struct image_header *)
+ CONFIG_SYS_UBOOT_BASE));
+}
+SPL_LOAD_IMAGE_METHOD("XIP", 0, BOOT_DEVICE_XIP, spl_xip);
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 3566223..f975eca 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -3,6 +3,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index f07a46b..ff3b0f8 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -3,6 +3,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_NAND_SUPPORT=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 333e204..27a4124 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -3,6 +3,7 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
CONFIG_TARGET_BRPPT1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index f558886..7353b2a 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -3,6 +3,8 @@
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
+CONFIG_TARGET_BRXRE1=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
@@ -57,6 +59,7 @@
CONFIG_USB_STORAGE=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_LCD=y
+# CONFIG_OMAP_WATCHDOG is not set
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index d813cc5..5c5b114 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -3,6 +3,7 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM43XX=y
CONFIG_TARGET_CM_T43=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 0e50b31..28fe82a 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -4,8 +4,9 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_DRACO=y
+CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
+CONFIG_TARGET_DRACO=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index b6911fd..aac8bfa 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -4,8 +4,9 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_ETAMIN=y
+CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
+CONFIG_TARGET_ETAMIN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
index 6e0a5e9..e328331 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep0020_defconfig
@@ -2,6 +2,7 @@
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_OMAP34XX=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
CONFIG_BOOTDELAY=3
@@ -14,8 +15,6 @@
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ONENAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
@@ -25,15 +24,8 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_UBI=y
CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index b5d14d2..c6f474a 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -31,5 +31,4 @@
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SYS_NS16550=y
-# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 67bdfd6..4d6e261 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -4,8 +4,9 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_PXM2=y
+CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=720
+CONFIG_TARGET_PXM2=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index f77d4d4..a3adce5 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -4,8 +4,9 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_RASTABAN=y
+CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
+CONFIG_TARGET_RASTABAN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index f09a67e..8acc7cc 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -4,8 +4,9 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_RUT=y
+CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
+CONFIG_TARGET_RUT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -73,3 +74,4 @@
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_SYS_CONSOLE_BG_COL=0xff
CONFIG_SYS_CONSOLE_FG_COL=0x00
+# CONFIG_OMAP_WATCHDOG is not set
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 4322aad..766b111 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -39,15 +39,10 @@
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_PINCTRL_STM32=y
-# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SPI=y
CONFIG_STM32_QSPI=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
-CONFIG_CLK=y
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_FULL is not set
-CONFIG_PINCTRL_STM32=y
CONFIG_RAM=y
CONFIG_STM32_SDRAM=y
CONFIG_DM_GPIO=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 914f70f..4c07de7 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -4,8 +4,9 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_THUBAN=y
+CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
+CONFIG_TARGET_THUBAN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index 6145675..23f131b 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -453,6 +453,32 @@
return 0;
}
+int blk_get_from_parent(struct udevice *parent, struct udevice **devp)
+{
+ struct udevice *dev;
+ enum uclass_id id;
+ int ret;
+
+ device_find_first_child(parent, &dev);
+ if (!dev) {
+ debug("%s: No block device found for parent '%s'\n", __func__,
+ parent->name);
+ return -ENODEV;
+ }
+ id = device_get_uclass_id(dev);
+ if (id != UCLASS_BLK) {
+ debug("%s: Incorrect uclass %s for block device '%s'\n",
+ __func__, uclass_get_name(id), dev->name);
+ return -ENOTBLK;
+ }
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+ *devp = dev;
+
+ return 0;
+}
+
int blk_find_max_devnum(enum if_type if_type)
{
struct udevice *dev;
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0dd4443..82b8d75 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -156,7 +156,7 @@
config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
- depends on RMOBILE
+ depends on ARCH_RMOBILE
help
Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 4dc3925..994d268 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -97,7 +97,7 @@
struct udevice *dev, *mmc_dev;
int ret;
- ret = blk_get_device(IF_TYPE_MMC, dev_num, &dev);
+ ret = blk_find_device(IF_TYPE_MMC, dev_num, &dev);
if (ret) {
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
@@ -108,7 +108,9 @@
mmc_dev = dev_get_parent(dev);
- return mmc_get_mmc_dev(mmc_dev);
+ struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
+
+ return mmc;
}
int get_mmc_num(void)
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
index 25224e2..d181b63 100644
--- a/drivers/mmc/sh_sdhi.c
+++ b/drivers/mmc/sh_sdhi.c
@@ -3,7 +3,7 @@
*
* SD/MMC driver for Renesas rmobile ARM SoCs.
*
- * Copyright (C) 2011,2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2011,2013-2017 Renesas Electronics Corporation
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* Copyright (C) 2008-2009 Renesas Solutions Corp.
*
@@ -29,6 +29,17 @@
unsigned char sd_error;
unsigned char detect_waiting;
};
+
+static inline void sh_sdhi_writeq(struct sh_sdhi_host *host, int reg, u64 val)
+{
+ writeq(val, host->addr + (reg << host->bus_shift));
+}
+
+static inline u64 sh_sdhi_readq(struct sh_sdhi_host *host, int reg)
+{
+ return readq(host->addr + (reg << host->bus_shift));
+}
+
static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val)
{
writew(val, host->addr + (reg << host->bus_shift));
@@ -261,6 +272,7 @@
long time;
unsigned short blocksize, i;
unsigned short *p = (unsigned short *)data->dest;
+ u64 *q = (u64 *)data->dest;
if ((unsigned long)p & 0x00000001) {
debug(DRIVER_NAME": %s: The data pointer is unaligned.",
@@ -281,8 +293,12 @@
host->wait_int = 0;
blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- for (i = 0; i < blocksize / 2; i++)
- *p++ = sh_sdhi_readw(host, SDHI_BUF0);
+ if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
+ for (i = 0; i < blocksize / 8; i++)
+ *q++ = sh_sdhi_readq(host, SDHI_BUF0);
+ else
+ for (i = 0; i < blocksize / 2; i++)
+ *p++ = sh_sdhi_readw(host, SDHI_BUF0);
time = sh_sdhi_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
@@ -297,6 +313,7 @@
long time;
unsigned short blocksize, i, sec;
unsigned short *p = (unsigned short *)data->dest;
+ u64 *q = (u64 *)data->dest;
if ((unsigned long)p & 0x00000001) {
debug(DRIVER_NAME": %s: The data pointer is unaligned.",
@@ -319,8 +336,12 @@
host->wait_int = 0;
blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- for (i = 0; i < blocksize / 2; i++)
- *p++ = sh_sdhi_readw(host, SDHI_BUF0);
+ if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
+ for (i = 0; i < blocksize / 8; i++)
+ *q++ = sh_sdhi_readq(host, SDHI_BUF0);
+ else
+ for (i = 0; i < blocksize / 2; i++)
+ *p++ = sh_sdhi_readw(host, SDHI_BUF0);
}
return 0;
@@ -332,6 +353,7 @@
long time;
unsigned short blocksize, i;
const unsigned short *p = (const unsigned short *)data->src;
+ const u64 *q = (const u64 *)data->src;
if ((unsigned long)p & 0x00000001) {
debug(DRIVER_NAME": %s: The data pointer is unaligned.",
@@ -356,8 +378,12 @@
host->wait_int = 0;
blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- for (i = 0; i < blocksize / 2; i++)
- sh_sdhi_writew(host, SDHI_BUF0, *p++);
+ if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
+ for (i = 0; i < blocksize / 8; i++)
+ sh_sdhi_writeq(host, SDHI_BUF0, *q++);
+ else
+ for (i = 0; i < blocksize / 2; i++)
+ sh_sdhi_writew(host, SDHI_BUF0, *p++);
time = sh_sdhi_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
@@ -372,6 +398,7 @@
long time;
unsigned short i, sec, blocksize;
const unsigned short *p = (const unsigned short *)data->src;
+ const u64 *q = (const u64 *)data->src;
debug("%s: blocks = %d, blocksize = %d\n",
__func__, data->blocks, data->blocksize);
@@ -388,8 +415,12 @@
host->wait_int = 0;
blocksize = sh_sdhi_readw(host, SDHI_SIZE);
- for (i = 0; i < blocksize / 2; i++)
- sh_sdhi_writew(host, SDHI_BUF0, *p++);
+ if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
+ for (i = 0; i < blocksize / 8; i++)
+ sh_sdhi_writeq(host, SDHI_BUF0, *q++);
+ else
+ for (i = 0; i < blocksize / 2; i++)
+ sh_sdhi_writew(host, SDHI_BUF0, *p++);
}
return 0;
@@ -458,6 +489,13 @@
else /* SD_SWITCH */
opc = SDHI_SD_SWITCH;
break;
+ case MMC_CMD_SEND_OP_COND:
+ opc = SDHI_MMC_SEND_OP_COND;
+ break;
+ case MMC_CMD_SEND_EXT_CSD:
+ if (data)
+ opc = SDHI_MMC_SEND_EXT_CSD;
+ break;
default:
break;
}
@@ -482,6 +520,7 @@
case MMC_CMD_READ_SINGLE_BLOCK:
case SDHI_SD_APP_SEND_SCR:
case SDHI_SD_SWITCH: /* SD_SWITCH */
+ case SDHI_MMC_SEND_EXT_CSD:
ret = sh_sdhi_single_read(host, data);
break;
default:
@@ -546,8 +585,6 @@
break;
}
- sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK));
-
host->wait_int = 0;
sh_sdhi_writew(host, SDHI_INFO1_MASK,
~INFO1M_RESP_END & sh_sdhi_readw(host, SDHI_INFO1_MASK));
@@ -557,6 +594,8 @@
INFO2M_RESP_TIMEOUT | INFO2M_ILA) &
sh_sdhi_readw(host, SDHI_INFO2_MASK));
+ sh_sdhi_writew(host, SDHI_CMD, (unsigned short)(opc & CMD_MASK));
+
time = sh_sdhi_wait_interrupt_flag(host);
if (!time)
return sh_sdhi_error_manage(host);
@@ -617,12 +656,18 @@
if (ret)
return -EINVAL;
- if (mmc->bus_width == 4)
- sh_sdhi_writew(host, SDHI_OPTION, ~OPT_BUS_WIDTH_1 &
- sh_sdhi_readw(host, SDHI_OPTION));
+ if (mmc->bus_width == 8)
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_8 | (~OPT_BUS_WIDTH_M &
+ sh_sdhi_readw(host, SDHI_OPTION)));
+ else if (mmc->bus_width == 4)
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_4 | (~OPT_BUS_WIDTH_M &
+ sh_sdhi_readw(host, SDHI_OPTION)));
else
- sh_sdhi_writew(host, SDHI_OPTION, OPT_BUS_WIDTH_1 |
- sh_sdhi_readw(host, SDHI_OPTION));
+ sh_sdhi_writew(host, SDHI_OPTION,
+ OPT_BUS_WIDTH_1 | (~OPT_BUS_WIDTH_M &
+ sh_sdhi_readw(host, SDHI_OPTION)));
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
@@ -653,6 +698,19 @@
.init = sh_sdhi_initialize,
};
+#ifdef CONFIG_RCAR_GEN3
+static struct mmc_config sh_sdhi_cfg = {
+ .name = DRIVER_NAME,
+ .ops = &sh_sdhi_ops,
+ .f_min = CLKDEV_INIT,
+ .f_max = CLKDEV_HS_DATA,
+ .voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+ .host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HS |
+ MMC_MODE_HS_52MHz,
+ .part_type = PART_TYPE_DOS,
+ .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
+};
+#else
static struct mmc_config sh_sdhi_cfg = {
.name = DRIVER_NAME,
.ops = &sh_sdhi_ops,
@@ -663,6 +721,7 @@
.part_type = PART_TYPE_DOS,
.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
};
+#endif
int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks)
{
@@ -687,7 +746,9 @@
host->addr = addr;
host->quirks = quirks;
- if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
+ if (host->quirks & SH_SDHI_QUIRK_64BIT_BUF)
+ host->bus_shift = 2;
+ else if (host->quirks & SH_SDHI_QUIRK_16BIT_BUF)
host->bus_shift = 1;
return ret;
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 150c68d..f948783 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -69,6 +69,7 @@
config SPL_PINCTRL_FULL
bool "Support full pin controllers in SPL"
depends on SPL_PINCTRL && SPL_OF_CONTROL
+ default n if TARGET_STM32F746_DISCO
default y
help
This option is an SPL-variant of the PINCTRL_FULL option.
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 3f50c12..e3f9e4d 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -188,6 +188,13 @@
The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
This driver binds the pmic children.
+config PMIC_LP87565
+ bool "Enable driver for Texas Instruments LP87565 PMIC"
+ depends on DM_PMIC
+ ---help---
+ The LP87565 is a PMIC containing a bunch of SMPS.
+ This driver binds the pmic children.
+
config POWER_MC34VR500
bool "Enable driver for Freescale MC34VR500 PMIC"
---help---
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f409e3a..f488799 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -21,6 +21,7 @@
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
obj-$(CONFIG_$(SPL_)PMIC_PALMAS) += palmas.o
obj-$(CONFIG_$(SPL_)PMIC_LP873X) += lp873x.o
+obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o
diff --git a/drivers/power/pmic/lp87565.c b/drivers/power/pmic/lp87565.c
new file mode 100644
index 0000000..782a46c
--- /dev/null
+++ b/drivers/power/pmic/lp87565.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2017 Texas Instruments Incorporated, <www.ti.com>
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp87565.h>
+#include <dm/device.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "buck", .driver = LP87565_BUCK_DRIVER },
+ { },
+};
+
+static int lp87565_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ int ret;
+
+ ret = dm_i2c_write(dev, reg, buff, len);
+ if (ret)
+ error("write error to device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static int lp87565_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ int ret;
+
+ ret = dm_i2c_read(dev, reg, buff, len);
+ if (ret)
+ error("read error from device: %p register: %#x!", dev, reg);
+
+ return ret;
+}
+
+static int lp87565_bind(struct udevice *dev)
+{
+ ofnode regulators_node;
+ int children;
+
+ regulators_node = dev_read_subnode(dev, "regulators");
+ if (!ofnode_valid(regulators_node)) {
+ debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ printf("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops lp87565_ops = {
+ .read = lp87565_read,
+ .write = lp87565_write,
+};
+
+static const struct udevice_id lp87565_ids[] = {
+ { .compatible = "ti,lp87565", .data = LP87565 },
+ { .compatible = "ti,lp87565-q1", .data = LP87565_Q1 },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_lp87565) = {
+ .name = "lp87565_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = lp87565_ids,
+ .bind = lp87565_bind,
+ .ops = &lp87565_ops,
+};
diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c
index c5e768a..911f639 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -96,7 +96,8 @@
int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
{
if ((dc_cntrl_reg != TPS65218_DCDC1) &&
- (dc_cntrl_reg != TPS65218_DCDC2))
+ (dc_cntrl_reg != TPS65218_DCDC2) &&
+ (dc_cntrl_reg != TPS65218_DCDC3))
return 1;
/* set voltage level */
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index ef057e0..f213487 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -149,3 +149,13 @@
This enables implementation of driver-model regulator uclass
features for REGULATOR LP873X and the family of LP873X PMICs.
The driver implements get/set api for: value and enable.
+
+config DM_REGULATOR_LP87565
+ bool "Enable driver for LP87565 PMIC regulators"
+ depends on PMIC_LP87565
+ ---help---
+ This enables implementation of driver-model regulator uclass
+ features for REGULATOR LP87565 and the family of LP87565 PMICs.
+ LP87565 series of PMICs have 4 single phase BUCKs that can also
+ be configured in multi phase modes. The driver implements
+ get/set api for value and enable.
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 3e01021..ce14d08 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -18,3 +18,4 @@
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_PALMAS) += palmas_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP873X) += lp873x_regulator.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_LP87565) += lp87565_regulator.o
diff --git a/drivers/power/regulator/lp87565_regulator.c b/drivers/power/regulator/lp87565_regulator.c
new file mode 100644
index 0000000..2a0b8ca
--- /dev/null
+++ b/drivers/power/regulator/lp87565_regulator.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2017
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Keerthy <j-keerthy@ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <dm.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/lp87565.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char lp87565_buck_ctrl1[LP87565_BUCK_NUM] = {0x2, 0x4, 0x6, 0x8, 0x2, 0x6};
+static const char lp87565_buck_vout[LP87565_BUCK_NUM] = {0xA, 0xC, 0xE, 0x10, 0xA, 0xE };
+
+static int lp87565_buck_enable(struct udevice *dev, int op, bool *enable)
+{
+ int ret;
+ unsigned int adr;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ adr = uc_pdata->ctrl_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP87565_BUCK_MODE_MASK;
+
+ if (ret)
+ *enable = true;
+ else
+ *enable = false;
+
+ return 0;
+ } else if (op == PMIC_OP_SET) {
+ if (*enable)
+ ret |= LP87565_BUCK_MODE_MASK;
+ else
+ ret &= ~LP87565_BUCK_MODE_MASK;
+ ret = pmic_reg_write(dev->parent, adr, ret);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int lp87565_buck_volt2val(int uV)
+{
+ if (uV > LP87565_BUCK_VOLT_MAX)
+ return -EINVAL;
+ else if (uV > 1400000)
+ return (uV - 1420000) / 20000 + 0x9E;
+ else if (uV > 730000)
+ return (uV - 735000) / 5000 + 0x18;
+ else if (uV >= 500000)
+ return (uV - 500000) / 10000;
+ else
+ return -EINVAL;
+}
+
+static int lp87565_buck_val2volt(int val)
+{
+ if (val > LP87565_BUCK_VOLT_MAX_HEX)
+ return -EINVAL;
+ else if (val > 0x9D)
+ return 1400000 + (val - 0x9D) * 20000;
+ else if (val > 0x17)
+ return 730000 + (val - 0x17) * 5000;
+ else if (val >= 0x0)
+ return 500000 + val * 10000;
+ else
+ return -EINVAL;
+}
+
+static int lp87565_buck_val(struct udevice *dev, int op, int *uV)
+{
+ unsigned int hex, adr;
+ int ret;
+ struct dm_regulator_uclass_platdata *uc_pdata;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+
+ if (op == PMIC_OP_GET)
+ *uV = 0;
+
+ adr = uc_pdata->volt_reg;
+
+ ret = pmic_reg_read(dev->parent, adr);
+ if (ret < 0)
+ return ret;
+
+ if (op == PMIC_OP_GET) {
+ ret &= LP87565_BUCK_VOLT_MASK;
+ ret = lp87565_buck_val2volt(ret);
+ if (ret < 0)
+ return ret;
+ *uV = ret;
+
+ return 0;
+ }
+
+ hex = lp87565_buck_volt2val(*uV);
+ if (hex < 0)
+ return hex;
+
+ ret &= 0x0;
+ ret = hex;
+
+ ret = pmic_reg_write(dev->parent, adr, ret);
+
+ return ret;
+}
+
+static int lp87565_buck_probe(struct udevice *dev)
+{
+ struct dm_regulator_uclass_platdata *uc_pdata;
+ int idx;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ uc_pdata->type = REGULATOR_TYPE_BUCK;
+
+ idx = dev->driver_data;
+ if (idx == 0 || idx == 1 || idx == 2 || idx == 3) {
+ debug("Single phase regulator\n");
+ } else if (idx == 23) {
+ idx = 5;
+ } else if (idx == 10) {
+ idx = 4;
+ } else {
+ printf("Wrong ID for regulator\n");
+ return -EINVAL;
+ }
+
+ uc_pdata->ctrl_reg = lp87565_buck_ctrl1[idx];
+ uc_pdata->volt_reg = lp87565_buck_vout[idx];
+
+ return 0;
+}
+
+static int buck_get_value(struct udevice *dev)
+{
+ int uV;
+ int ret;
+
+ ret = lp87565_buck_val(dev, PMIC_OP_GET, &uV);
+ if (ret)
+ return ret;
+
+ return uV;
+}
+
+static int buck_set_value(struct udevice *dev, int uV)
+{
+ return lp87565_buck_val(dev, PMIC_OP_SET, &uV);
+}
+
+static bool buck_get_enable(struct udevice *dev)
+{
+ bool enable = false;
+ int ret;
+
+
+ ret = lp87565_buck_enable(dev, PMIC_OP_GET, &enable);
+ if (ret)
+ return ret;
+
+ return enable;
+}
+
+static int buck_set_enable(struct udevice *dev, bool enable)
+{
+ return lp87565_buck_enable(dev, PMIC_OP_SET, &enable);
+}
+
+static const struct dm_regulator_ops lp87565_buck_ops = {
+ .get_value = buck_get_value,
+ .set_value = buck_set_value,
+ .get_enable = buck_get_enable,
+ .set_enable = buck_set_enable,
+};
+
+U_BOOT_DRIVER(lp87565_buck) = {
+ .name = LP87565_BUCK_DRIVER,
+ .id = UCLASS_REGULATOR,
+ .ops = &lp87565_buck_ops,
+ .probe = lp87565_buck_probe,
+};
diff --git a/drivers/power/regulator/palmas_regulator.c b/drivers/power/regulator/palmas_regulator.c
index 399f7a5..841c03a 100644
--- a/drivers/power/regulator/palmas_regulator.c
+++ b/drivers/power/regulator/palmas_regulator.c
@@ -377,7 +377,11 @@
uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
uc_pdata->volt_reg = palmas_smps_volt[type][idx];
break;
-
+ case 12:
+ idx = 0;
+ uc_pdata->ctrl_reg = palmas_smps_ctrl[type][idx];
+ uc_pdata->volt_reg = palmas_smps_volt[type][idx];
+ break;
default:
printf("Wrong ID for regulator\n");
}
diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c
index dae1b3c..4b73d17 100644
--- a/drivers/rtc/ds1337.c
+++ b/drivers/rtc/ds1337.c
@@ -150,11 +150,11 @@
* SQW/INTB* pin and program it for 32,768 Hz output. Note that
* according to the datasheet, turning on the square wave output
* increases the current drain on the backup battery from about
- * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
+ * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
* off the OSC output.
*/
-#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
+#ifdef CONFIG_RTC_DS1337_NOOSC
#define RTC_DS1337_RESET_VAL \
(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#else
@@ -162,16 +162,16 @@
#endif
void rtc_reset (void)
{
-#ifdef CONFIG_SYS_RTC_DS1337
+#ifdef CONFIG_RTC_DS1337
rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
-#elif defined CONFIG_SYS_RTC_DS1388
+#elif defined CONFIG_RTC_DS1388
rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
#endif
-#ifdef CONFIG_SYS_DS1339_TCR_VAL
- rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
+#ifdef CONFIG_RTC_DS1339_TCR_VAL
+ rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
#endif
-#ifdef CONFIG_SYS_DS1388_TCR_VAL
- rtc_write(RTC_TC_REG_ADDR, CONFIG_SYS_DS1388_TCR_VAL);
+#ifdef CONFIG_RTC_DS1388_TCR_VAL
+ rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
#endif
}
diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c
index bdabf87..483e4ba 100644
--- a/drivers/serial/serial_stm32x7.c
+++ b/drivers/serial/serial_stm32x7.c
@@ -93,6 +93,9 @@
}
#endif
+ /* Disable usart-> disable overrun-> enable usart */
+ clrbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
+ setbits_le32(&usart->cr3, USART_CR3_OVRDIS);
setbits_le32(&usart->cr1, USART_CR1_RE | USART_CR1_TE | USART_CR1_UE);
return 0;
diff --git a/drivers/serial/serial_stm32x7.h b/drivers/serial/serial_stm32x7.h
index 6190d67..8c02548 100644
--- a/drivers/serial/serial_stm32x7.h
+++ b/drivers/serial/serial_stm32x7.h
@@ -27,6 +27,8 @@
#define USART_CR1_TE (1 << 3)
#define USART_CR1_UE (1 << 0)
+#define USART_CR3_OVRDIS (1 << 12)
+
#define USART_SR_FLAG_RXNE (1 << 5)
#define USART_SR_FLAG_TXE (1 << 7)
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 47078fd..f77da2e 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -426,7 +426,9 @@
writel(~0UL, ®s->lcdc_baseidr);
/* Setup the DMA descriptor, this descriptor will loop to itself */
- desc = (struct lcd_dma_desc *)(uc_plat->base - 16);
+ desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
+ if (!desc)
+ return;
desc->address = (u32)uc_plat->base;
@@ -436,7 +438,9 @@
desc->next = (u32)desc;
/* Flush the DMA descriptor if we enabled dcache */
- flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+ flush_dcache_range((u32)desc,
+ ALIGN(((u32)desc + sizeof(*desc)),
+ CONFIG_SYS_CACHELINE_SIZE));
writel(desc->address, ®s->lcdc_baseaddr);
writel(desc->control, ®s->lcdc_basectrl);
diff --git a/drivers/video/rockchip/rk_hdmi.h b/drivers/video/rockchip/rk_hdmi.h
index 501ed3a..ec39668 100644
--- a/drivers/video/rockchip/rk_hdmi.h
+++ b/drivers/video/rockchip/rk_hdmi.h
@@ -23,10 +23,54 @@
void *grf;
};
+/**
+ * rk_hdmi_read_edid() - read the attached HDMI/DVI monitor's EDID
+ *
+ * N.B.: The buffer should be large enough to hold 2 EDID blocks, as
+ * this function calls dw_hdmi_read_edid, which ignores buf_size
+ * argument and assumes that there's always enough space for 2
+ * EDID blocks.
+ *
+ * @dev: device
+ * @buf: output buffer for the EDID
+ * @buf_size: number of bytes in the buffer
+ * @return number of bytes read if OK, -ve if something went wrong
+ */
int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size);
+
+/**
+ * rk_hdmi_probe_regulators() - probe (autoset + enable) regulators
+ *
+ * Probes a list of regulators by performing autoset and enable
+ * operations on them. The list of regulators is an array of string
+ * pointers and any individual regulator-probe may fail without
+ * counting as an error.
+ *
+ * @dev: device
+ * @names: array of string-pointers to regulator names to probe
+ * @cnt: number of elements in the 'names' array
+ */
void rk_hdmi_probe_regulators(struct udevice *dev,
const char * const *names, int cnt);
+/**
+ * rk_hdmi_ofdata_to_platdata() - common ofdata_to_platdata implementation
+ *
+ * @dev: device
+ * @return 0 if OK, -ve if something went wrong
+ */
int rk_hdmi_ofdata_to_platdata(struct udevice *dev);
+
+/**
+ * rk_hdmi_probe() - common probe implementation
+ *
+ * Performs the following, common initialisation steps:
+ * 1. checks for HPD (i.e. a HDMI monitor being attached)
+ * 2. initialises the Designware HDMI core
+ * 3. initialises the Designware HDMI PHY
+ *
+ * @dev: device
+ * @return 0 if OK, -ve if something went wrong
+ */
int rk_hdmi_probe(struct udevice *dev);
#endif
diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h
index 9bda514..b2b29c4 100644
--- a/drivers/video/rockchip/rk_vop.h
+++ b/drivers/video/rockchip/rk_vop.h
@@ -25,8 +25,42 @@
void (*set_pin_polarity)(struct udevice *, enum vop_modes, u32);
};
+/**
+ * rk_vop_probe() - common probe implementation
+ *
+ * Performs the rk_display_init on each port-subnode until finding a
+ * working port (or returning an error if none of the ports could be
+ * successfully initialised).
+ *
+ * @dev: device
+ * @return 0 if OK, -ve if something went wrong
+ */
int rk_vop_probe(struct udevice *dev);
+
+/**
+ * rk_vop_bind() - common bind implementation
+ *
+ * Sets the plat->size field to the amount of memory to be reserved for
+ * the framebuffer: this is always
+ * (32 BPP) x VIDEO_ROCKCHIP_MAX_XRES x VIDEO_ROCKCHIP_MAX_YRES
+ *
+ * @dev: device
+ * @return 0 (always OK)
+ */
int rk_vop_bind(struct udevice *dev);
+
+/**
+ * rk_vop_probe_regulators() - probe (autoset + enable) regulators
+ *
+ * Probes a list of regulators by performing autoset and enable
+ * operations on them. The list of regulators is an array of string
+ * pointers and any individual regulator-probe may fail without
+ * counting as an error.
+ *
+ * @dev: device
+ * @names: array of string-pointers to regulator names to probe
+ * @cnt: number of elements in the 'names' array
+ */
void rk_vop_probe_regulators(struct udevice *dev,
const char * const *names, int cnt);
diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile
index dbaab61..0d64c20 100644
--- a/drivers/video/sunxi/Makefile
+++ b/drivers/video/sunxi/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve.o ../videomodes.o
+obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o tve_common.o ../videomodes.o
obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c
index 9a32c3a..ee67764 100644
--- a/drivers/video/sunxi/sunxi_de2.c
+++ b/drivers/video/sunxi/sunxi_de2.c
@@ -56,7 +56,7 @@
}
static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
- int bpp, ulong address)
+ int bpp, ulong address, bool is_composite)
{
ulong de_mux_base = (mux == 0) ?
SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
@@ -72,6 +72,9 @@
(struct de_ui *)(de_mux_base +
SUNXI_DE2_MUX_CHAN_REGS +
SUNXI_DE2_MUX_CHAN_SZ * 1);
+ struct de_csc * const de_csc_regs =
+ (struct de_csc *)(de_mux_base +
+ SUNXI_DE2_MUX_DCSC_REGS);
u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
int channel;
u32 format;
@@ -128,7 +131,27 @@
writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
- writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS);
+
+ if (is_composite) {
+ /* set CSC coefficients */
+ writel(0x107, &de_csc_regs->coef11);
+ writel(0x204, &de_csc_regs->coef12);
+ writel(0x64, &de_csc_regs->coef13);
+ writel(0x4200, &de_csc_regs->coef14);
+ writel(0x1f68, &de_csc_regs->coef21);
+ writel(0x1ed6, &de_csc_regs->coef22);
+ writel(0x1c2, &de_csc_regs->coef23);
+ writel(0x20200, &de_csc_regs->coef24);
+ writel(0x1c2, &de_csc_regs->coef31);
+ writel(0x1e87, &de_csc_regs->coef32);
+ writel(0x1fb7, &de_csc_regs->coef33);
+ writel(0x20200, &de_csc_regs->coef34);
+
+ /* enable CSC unit */
+ writel(1, &de_csc_regs->csc_ctl);
+ } else {
+ writel(0, &de_csc_regs->csc_ctl);
+ }
switch (bpp) {
case 16:
@@ -153,7 +176,7 @@
static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
enum video_log2_bpp l2bpp,
- struct udevice *disp, int mux)
+ struct udevice *disp, int mux, bool is_composite)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
@@ -183,7 +206,7 @@
}
sunxi_de2_composer_init();
- sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase);
+ sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite);
ret = display_enable(disp, 1 << l2bpp, &timing);
if (ret) {
@@ -204,7 +227,6 @@
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct udevice *disp;
int ret;
- int mux;
/* Before relocation we don't need to do anything */
if (!(gd->flags & GD_FLG_RELOC))
@@ -212,17 +234,31 @@
ret = uclass_find_device_by_name(UCLASS_DISPLAY,
"sunxi_dw_hdmi", &disp);
+ if (!ret) {
+ int mux;
+ if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
+ mux = 0;
+ else
+ mux = 1;
+
+ ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux,
+ false);
+ if (!ret) {
+ video_set_flush_dcache(dev, 1);
+ return 0;
+ }
+ }
+
+ debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
+
+ ret = uclass_find_device_by_name(UCLASS_DISPLAY,
+ "sunxi_tve", &disp);
if (ret) {
- debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
+ debug("%s: tv not found (ret=%d)\n", __func__, ret);
return ret;
}
- if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
- mux = 0;
- else
- mux = 1;
-
- ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux);
+ ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true);
if (ret)
return ret;
diff --git a/drivers/video/sunxi/tve.c b/drivers/video/sunxi/tve_common.c
similarity index 100%
rename from drivers/video/sunxi/tve.c
rename to drivers/video/sunxi/tve_common.c
diff --git a/include/blk.h b/include/blk.h
index a128ee4..ef29a07 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -377,6 +377,13 @@
*/
int blk_select_hwpart(struct udevice *dev, int hwpart);
+/**
+ * blk_get_from_parent() - obtain a block device by looking up its parent
+ *
+ * All devices with
+ */
+int blk_get_from_parent(struct udevice *parent, struct udevice **devp);
+
#else
#include <errno.h>
/*
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index b2feccf..8579290 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -311,7 +311,7 @@
#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_RTC_DS1337_NOOSC
+#define CONFIG_RTC_DS1337_NOOSC
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h
index 7907310..8d0e0ea 100644
--- a/include/configs/bur_am335x_common.h
+++ b/include/configs/bur_am335x_common.h
@@ -12,7 +12,6 @@
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
-#define CONFIG_AM33XX
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index 1e63098..7b5ca0d 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -9,7 +9,6 @@
#ifndef __CONFIG_CM_T43_H
#define __CONFIG_CM_T43_H
-#define CONFIG_AM43XX
#define CONFIG_CM_T43
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */
@@ -21,7 +20,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM1 0x44e09000
-#ifdef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#endif
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 0a8096c..5f11895 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -110,7 +110,7 @@
(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
- (10 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
+ (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
(2 << DV_DDR_SDTMR2_CKE_SHIFT))
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index b5705b7..21029d1 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -14,8 +14,6 @@
#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
#define __CONFIG_SIEMENS_AM33X_COMMON_H
-#define CONFIG_AM33XX
-
#include <asm/arch/omap.h>
#define CONFIG_DMA_COHERENT
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 1ee5815..4e0edcb 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -10,14 +10,20 @@
#define CONFIG_SYS_FLASH_BASE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR 0x20050000
-#define CONFIG_SYS_TEXT_BASE 0x08000000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_TEXT_BASE 0x08008000
+#define CONFIG_SYS_LOAD_ADDR 0x08008000
+#else
+#define CONFIG_SYS_TEXT_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LOAD_ADDR 0xC0400000
+#define CONFIG_LOADADDR 0xC0400000
+#endif
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_SYS_LOAD_ADDR 0xC0400000
-#define CONFIG_LOADADDR 0xC0400000
#define CONFIG_SYS_MAX_FLASH_SECT 8
#define CONFIG_SYS_MAX_FLASH_BANKS 1
@@ -69,4 +75,23 @@
#define CONFIG_CMD_CACHE
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_DISPLAY_BOARDINFO
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_SPL_LEN 0x00008000
+#define CONFIG_SYS_UBOOT_START 0x080083FD
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_SPL_LEN)
+
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
+ 0x1C0000)
+#endif
+/* For SPL ends */
+
#endif /* __CONFIG_H */
diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h
index 4ab4c65..4e99cdb 100644
--- a/include/configs/tqma6_wru4.h
+++ b/include/configs/tqma6_wru4.h
@@ -29,7 +29,7 @@
#define CONFIG_SYS_RTC_BUS_NUM 2
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* Turn off RTC square-wave output to save battery */
-#define CONFIG_SYS_RTC_DS1337_NOOSC
+#define CONFIG_RTC_DS1337_NOOSC
/* LED */
diff --git a/include/image.h b/include/image.h
index 8d380e0..fcfe730 100644
--- a/include/image.h
+++ b/include/image.h
@@ -785,7 +785,8 @@
}
static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
{
- return (image_get_arch(hdr) == arch);
+ return (image_get_arch(hdr) == arch) ||
+ (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
}
static inline int image_check_os(const image_header_t *hdr, uint8_t os)
{
diff --git a/include/power/lp87565.h b/include/power/lp87565.h
new file mode 100644
index 0000000..5160f5d
--- /dev/null
+++ b/include/power/lp87565.h
@@ -0,0 +1,12 @@
+#define LP87565 0x0
+#define LP87565_Q1 0x1
+
+#define LP87565_BUCK_NUM 6
+
+/* Drivers name */
+#define LP87565_BUCK_DRIVER "lp87565_buck"
+
+#define LP87565_BUCK_VOLT_MASK 0xFF
+#define LP87565_BUCK_VOLT_MAX_HEX 0xFF
+#define LP87565_BUCK_VOLT_MAX 3360000
+#define LP87565_BUCK_MODE_MASK 0x80
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 69a49f7..cb07ea5 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -38,6 +38,7 @@
TPS65217_DEFLS1,
TPS65217_DEFLS2,
TPS65217_ENABLE,
+ TPS65217_RESERVED0, /* no 0x17 register available */
TPS65217_DEFUVLO,
TPS65217_SEQ1,
TPS65217_SEQ2,
diff --git a/include/power/tps65218.h b/include/power/tps65218.h
index e3538e2..43b9c9a 100644
--- a/include/power/tps65218.h
+++ b/include/power/tps65218.h
@@ -63,6 +63,7 @@
#define TPS65218_DCDC_VOLT_SEL_1200MV 0x23
#define TPS65218_DCDC_VOLT_SEL_1260MV 0x29
#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
+#define TPS65218_DCDC3_VOLT_SEL_1350MV 0x12
#define TPS65218_CC_STAT (BIT(0) | BIT(1))
#define TPS65218_STATE (BIT(2) | BIT(3))
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index c8cf428..2126a88 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2264,9 +2264,12 @@
CONFIG_RSK7269
CONFIG_RTC_DS1307
CONFIG_RTC_DS1337
+CONFIG_RTC_DS1337_NOOSC
CONFIG_RTC_DS1338
+CONFIG_RTC_DS1339_TCR_VAL
CONFIG_RTC_DS1374
CONFIG_RTC_DS1388
+CONFIG_RTC_DS1388_TCR_VAL
CONFIG_RTC_DS1556
CONFIG_RTC_DS174x
CONFIG_RTC_DS3231
@@ -3369,8 +3372,6 @@
CONFIG_SYS_DRAM_BASE
CONFIG_SYS_DRAM_SIZE
CONFIG_SYS_DRAM_TEST
-CONFIG_SYS_DS1339_TCR_VAL
-CONFIG_SYS_DS1388_TCR_VAL
CONFIG_SYS_DSPIC_TEST_ADDR
CONFIG_SYS_DSPIC_TEST_MASK
CONFIG_SYS_DSPI_CS0
@@ -5501,9 +5502,6 @@
CONFIG_SYS_RTCSC
CONFIG_SYS_RTC_BUS_NUM
CONFIG_SYS_RTC_CNT
-CONFIG_SYS_RTC_DS1337
-CONFIG_SYS_RTC_DS1337_NOOSC
-CONFIG_SYS_RTC_DS1388
CONFIG_SYS_RTC_OSCILLATOR
CONFIG_SYS_RTC_PL031_BASE
CONFIG_SYS_RTC_REG_BASE_ADDR
diff --git a/test/dm/blk.c b/test/dm/blk.c
index 5c5eb82..923e8d9 100644
--- a/test/dm/blk.c
+++ b/test/dm/blk.c
@@ -150,3 +150,21 @@
return 0;
}
DM_TEST(dm_test_blk_devnum, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can get a block from its parent */
+static int dm_test_blk_get_from_parent(struct unit_test_state *uts)
+{
+ struct udevice *dev, *blk;
+
+ ut_assertok(uclass_get_device(UCLASS_MMC, 0, &dev));
+ ut_assertok(blk_get_from_parent(dev, &blk));
+
+ ut_assertok(uclass_get_device(UCLASS_I2C, 0, &dev));
+ ut_asserteq(-ENOTBLK, blk_get_from_parent(dev, &blk));
+
+ ut_assertok(uclass_get_device(UCLASS_GPIO, 0, &dev));
+ ut_asserteq(-ENODEV, blk_get_from_parent(dev, &blk));
+
+ return 0;
+}
+DM_TEST(dm_test_blk_get_from_parent, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index edef560..5830549 100644
--- a/tools/kwbimage.c
+++ b/tools/kwbimage.c
@@ -24,7 +24,7 @@
#include <openssl/err.h>
#include <openssl/evp.h>
-#if OPENSSL_VERSION_NUMBER < 0x10100000L
+#if OPENSSL_VERSION_NUMBER < 0x10100000L || defined(LIBRESSL_VERSION_NUMBER)
static void RSA_get0_key(const RSA *r,
const BIGNUM **n, const BIGNUM **e, const BIGNUM **d)
{