powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release. For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index f1f80f7..6aca166 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -392,6 +392,12 @@
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+ if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+ (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+ puts("N/A\n");
+ goto skip_l2;
+ }
+
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
@@ -412,6 +418,8 @@
;
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
}
+
+skip_l2:
#else
puts("disabled\n");
#endif